Publication Details
Towards Low Power Approximate DCT Architecture for HEVC Standard
Mrázek Vojtěch, Ing., Ph.D. (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Genetic programming, relaxed equivalence, approximate computing, HEVC, DCT
Video processing performed directly on IoT nodes is one of the most performance as well as energy demanding applications for current IoT technology. In order to support realtime high-definition video, energy-reduction optimizations have to be introduced at all levels of the video processing chain. This paper deals with an efficient implementation of Discrete Cosine Transform (DCT) blocks employed in video compression based on the High Efficiency Video Coding (HEVC) standard. The proposed multiplierless 4-input DCT implementations contain approximate adders and subtractors that were obtained using genetic programming. In order to manage the complexity of evolutionary approximation and provide formal guarantees in terms of errors of key circuit components, the worst and average errors were determined exactly by means of Binary decision diagrams. Under conditions of our experiments, approximate 4- input DCTs show better quality/power trade-offs than relevant implementations available in the literature. For example, 25% power reduction for the same error was obtained in comparison with a recent highly optimised implementation.
@inproceedings{BUT134715,
author="Zdeněk {Vašíček} and Vojtěch {Mrázek} and Lukáš {Sekanina}",
title="Towards Low Power Approximate DCT Architecture for HEVC Standard",
booktitle="Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)",
year="2017",
pages="1576--1581",
publisher="European Design and Automation Association",
address="Lausanne",
doi="10.23919/DATE.2017.7927241",
isbn="978-3-9815370-9-3",
url="https://www.fit.vut.cz/research/publication/11299/"
}