Publication Details
Evolutionary Functional Approximation of Circuits Implemented into FPGAs
Mrázek Vojtěch, Ing., Ph.D. (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
functional approximation
evolutionary algorithm
equivalence
FPGA synthesis
In many applications it is acceptable to allow a small error in the result if
significant improvements are obtained in terms of performance, area or energy
efficiency. Exploiting this principle is particularly important for FPGA-based
solutions that are inherently subject to many resources- oriented constraints.
This paper devises an automated method that enables to approximate circuit
components which are often implemented in multiple instances in FPGA-based
accelerators. The approximation process starts with a fully functional gate-level
circuit, which is approximated by means of Cartesian Genetic Programming
reflecting the error metric and constraints formulated by the user. The evolved
circuits are then implemented for a particular FPGA by common FPGA synthesis and
optimization tools. It is shown using five different FPGA tools, that the
approximations obtained by CGP working at the gate level are preserved at the
level look-up tables of FPGAs. The proposed method is evaluated in the task of
8-bit adder, 8-bit multiplier, 9-input median and 25-input median
approximation.
@inproceedings{BUT131010,
author="Zdeněk {Vašíček} and Vojtěch {Mrázek} and Lukáš {Sekanina}",
title="Evolutionary Functional Approximation of Circuits Implemented into FPGAs",
booktitle="2016 IEEE Symposium Series on Computational Intelligence",
year="2016",
pages="1--8",
publisher="Institute of Electrical and Electronics Engineers",
address="Athens",
doi="10.1109/SSCI.2016.7850173",
isbn="978-1-5090-4240-1",
url="https://www.fit.vut.cz/research/publication/11243/"
}