Publication Details
FPGA Prototyping and Accelerated Verification of ASIPs
Zachariášová Marcela, Ing., Ph.D. (DCSY)
Čekan Ondřej, Ing., Ph.D. (UFYZ)
Kotásek Zdeněk, doc. Ing., CSc.
UVM, Acceleration, FPGA Prototyping, ASIP
In current SoC verification, the trend is to create verification solutions that are tailored to specific issues in SoC or to specific architectures. The reason is that the complexity of these systems makes it difficult to use general verification approaches such as formal or simulation-based verification. This paper presents a solution that is targeted to one particular area - Application-Specific Instruction-Set Processors (ASIP) and multi-processor systems containing several ASIPs. We propose automated FPGA prototyping and accelerated verification of these systems while the accelerated verification environment corresponds to the principles of UVM (Universal Verification Methodology) therefore can easily be integrated. Automated generation of verification environments and acceleration of verification runnning on a real hardware platform makes this solution very unique and beneficial, not only in speed, but also in debugging specific hardware issues.
@inproceedings{BUT119854,
author="Jakub {Podivínský} and Marcela {Zachariášová} and Ondřej {Čekan} and Zdeněk {Kotásek}",
title="FPGA Prototyping and Accelerated Verification of ASIPs",
booktitle="IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems",
year="2015",
pages="145--148",
publisher="IEEE Computer Society",
address="Belgrade",
doi="10.1109/DDECS.2015.33",
isbn="978-1-4799-6780-3",
url="https://www.fit.vut.cz/research/publication/10881/"
}