Project Details

Formální postupy v diagnostice číslicových obvodů - verifikace testovatelného návrhu

Project Period: 1. 1. 2001 – 31. 12. 2003

Project Type: grant

Code: GA102/01/1531

Agency: Czech Science Foundation

Program: Standardní projekty

English title
Formal Approaches in Digital Design Diagnostics - Testable Design Verification
Type
grant
Keywords

testable design synthesis, digital circuit testability verification

Abstract

The growing complexity of integrated circuits confronts the manufacturers with the problem of testability. The implementation of diagnostic principles has become an integral part of the process of digital circuit synthesis. During the synthesis the topics of testability are evaluated simultaneously with the synthesis - e. g. full scan, partial scan or BIST methods. Different aspects of the circuit design are evaluated and the controllability/observability of the inputs/outputs of internal elements of the unit under design is an important feature. The diagnostic methodologies utilized during the circuit synthesis are based on heuristic approaches during which the structure of the circuit is analysed. These heuristic approaches are different for different types of circuits.The goal of this project is the development of formal tools which can be used to represent diagnostic features of a circuit and its internal elements, based on theory of sets, theory of graphs and mathematical logic concepts. The applicability of the formal tools will be verified on benchmark circuits and on circuits developed for practical applications. Together with this main theme the research into analytical approaches will be made. The results gained for both approaches will be currently compared. The possibility of combining both approaches will also be verified.

Team members
Kotásek Zdeněk, doc. Ing., CSc. – research leader
Drábek Vladimír, doc. Ing., CSc. (FIT)
Růžička Richard, doc. Ing., Ph.D., MBA (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Strnadel Josef, Ing., Ph.D. (DCSY)
Zbořil František, doc. Ing., CSc. (DITS)
Publications

2003

  • KOTÁSEK, Z.; MIKA, D.; STRNADEL, J. Proceeding of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. Proceeding of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. Poznaň: Publishing House of Poznan University of Technology, 2003. p. 233-238. ISBN: 83-7143-557-6. Detail
  • KOTÁSEK, Z.; MIKA, D.; STRNADEL, J. Test scheduling for embedded systems. Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003. Belek: IEEE Computer Society Press, 2003. p. 463-467. ISBN: 0-7695-2003-0. Detail
  • KOTÁSEK, Z.; TUPEC, P.; URBIŠ, H. Testing PCBs Based on Boundary Scan. Proceedings of International Carpathian Control Conference. Košice: The University of Technology Košice, 2003. p. 119-122. ISBN: 80-7099-509-2. Detail
  • KOTÁSEK, Z.; URBIŠ, H. USB-to-IDE Adapter Design and Implementation. 6th International Workshopn on Electronics, Control, Measurment and Signals. Liberec: Liberec University of Technology, 2003. p. 315-319. ISBN: 80-7083-708-X. Detail
  • MIKA, D. Uplatnění formálních postupů při návrhu řadiče testu číslicového systému. Počítačové Architektury & Diagnostika Pracovní seminář pro studenty doktorského studia Sborník příspěvků. Brno: Fakulta informačních technologií VUT v Brně, 2003. s. 17-23. ISBN: 80-214-2471-0. Detail
  • MIKA, D.; KOTÁSEK, Z. Proc. of IFAC Workshop on Programmable Devices and Systems Conference. Proc. of IFAC Workshop on Programmable Devices and Systems Conference. Ostrava: Faculty of Electrical Engineering and Computer Science, VSB-TU Ostrava, 2003. p. 447-452. ISBN: 0-08-044130-0. Detail
  • RŮŽIČKA, R. Testable Design Verification Using Petri Nets. Proceedings of Euromicro Symposium on Digital System Design 2003. Los Alamitos, CA: IEEE Computer Society Press, 2003. p. 304-311. ISBN: 0-7695-2003-0. Detail
  • RŮŽIČKA, R.; ZBOŘIL, F. Representation of Datapath Structure in Predicate Logic and its Implementation in Prolog. Proceedings of International Carpathian Control Conference. Košice: The University of Technology Košice, 2003. p. 727-730. ISBN: 80-7099-509-2. Detail
  • SEKANINA, L. Evolvable Components - From Theory to Hardware Implementations. Natural Computing Series. Natural Computing Series. Berlin: Springer Verlag, 2003. 194 p. ISBN: 3-540-40377-9. Detail
  • SEKANINA, L. From Implementations to a General Concept of Evolvable Machines. Lecture Notes in Computer Science, 2003, vol. 2003, no. 2610, p. 424-433. ISSN: 0302-9743. Detail
  • SEKANINA, L. Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware. Lecture Notes in Computer Science, 2003, vol. 2003, no. 2606, p. 186-197. ISSN: 0302-9743. Detail
  • SEKANINA, L.; RŮŽIČKA, R. Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers. The 2003 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2003. p. 135-144. ISBN: 0-7695-1977-6. Detail
  • SEKANINA, L.; RŮŽIČKA, R. On the Automatic Design of Testable Circuits. Proceedings of IEEE Workshop on Design nad Diagnostics of Electronic Circuits and Systems. Poznań: Publishing House of Poznan University of Technology, 2003. p. 299-300. ISBN: 83-7143-557-6. Detail
  • SLLAME, A. A Pipeline Scheduling Algorithm for High-Level Synthesis. Proc. of IFAC Workshop on Programmable Devices and Systems Conference. Ostrava: Elsevier Science, 2003. p. 178-183. ISBN: 0-08-044130-0. Detail
  • STRNADEL, J. Algebraic Analysis of Feedback Loop Dependencies in Order of Improving RTL Digital Circuit Testability. Proceedings of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. Poznan: Publishing House of Poznan University of Technology, 2003. p. 303-304. ISBN: 83-7143-557-6. Detail
  • STRNADEL, J. Analýza a zlepšení testovatelnosti RTL číslicového obvodu. Sborník příspěvků ze semináře Počítačové Architektury & Diagnostika. Brno: Fakulta informačních technologií VUT v Brně, 2003. s. 24-29. ISBN: 80-214-2471-0. Detail
  • STRNADEL, J. Nested Loops Degree Impact on RTL Digital Circuit Testability. Programmable Devices and Systems. Oxford: Elsevier Science, 2003. p. 202-207. ISBN: 0-08-044130-0. Detail
  • STRNADEL, J. Scan Layout Encoding by Means of a Binary String. Proceedings of 37th International Conference on Modelling and Simulation of Systems. Ostrava: 2003. p. 115-122. ISBN: 80-85988-86-0. Detail

2002

  • DRÁBEK, V.; SEKANINA, L. Basic Principles of Bio-Inspired Approaches to Fault Tolerance: Tutorial. Design for Test of Systems on Chip: Digital Test. Tallinn: Tallinn University of Technology, 2002. p. 1-48. ISBN: 0000-00-000-0. Detail
  • MIKA, D.; KOTÁSEK, Z.; STRNADEL, J. Test Controller Design Based on VHDL Source File Analysis. Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002. VIENALA Press, Edition: 55. Letná 42, 040 01 TU Košice: The University of Technology Košice, 2002. p. 135-141. ISBN: 80-7099-879-2. Detail
  • RŮŽIČKA, R. The Formal Approach to the RTL Test Application Problem Using Petri Nets. Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems 2002. Brno: Faculty of Information Technology BUT, 2002. p. 78-86. ISBN: 80-214-2094-4. Detail
  • RŮŽIČKA, R. VHDL Circuit Description Transparency Analysis. Proceedings of the Fifth International Scientific Conference Electronic Computers and Informatics 2002. Košice: Faculty of Electrical Engineering and Informatics, University of Technology Košice, 2002. p. 194-199. ISBN: 80-7099-879-2. Detail
  • SEKANINA, L. Evolution of digital circuits operating as image filters in dynamically changing environment. Mendel 2002 - 8th International Conference on Soft Computing. Brno: Brno University of Technology, 2002. p. 33-38. ISBN: 80-214-2135-5. Detail
  • SEKANINA, L. Evolvable Computational Machines: Formal Approach. Intelligent Technologies - Theory and Applications, E-ISCI 2002. Frontiers in Artificial Intelligence and Applications. Amsterdam: IOS Press, 2002. p. 166-172. ISBN: 1-58603-256-9. Detail
  • SEKANINA, L. Nanostructures and bio-inspired computer engineering (Abstract). Nano'02 (Abstracts). Brno: Akademické nakladatelství CERM, 2002. p. 74-74. ISBN: 80-7204-258-0. Detail
  • SEKANINA, L. Nanostructures and bio-inspired computer engineering. Proceedings of Nano02. Ostrava: Repronis, 2002. p. 233-236. ISBN: 80-7329-027-8. Detail
  • SEKANINA, L. Image Filter Design with Evolvable Hardware. Lecture Notes in Computer Science, 2002, vol. 2002, no. 2279, p. 255-266. ISSN: 0302-9743. Detail
  • SEKANINA, L.; DRÁBEK, V. A Survey of Bioinspired Methods for Design of Fault Tolerant Reconfigurable Architectures. Proc. of the 8th Biennial Baltic Electronics Conference. Tallinn: Tallinn University of Technology, 2002. p. 355-358. ISBN: 9985-59-292-1. Detail
  • SEKANINA, L.; DRÁBEK, V. Automatic Design of Image Operators Using Evolvable Hardware. Proc. of 5th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Brno: Brno University of Technology, 2002. p. 132-139. ISBN: 80-214-2094-4. Detail
  • SEKANINA, L.; DRÁBEK, V. Soft-hardware. Vesmír, 2002, roč. 81, č. 7, s. 393-395. ISSN: 0042-4544. Detail
  • SLLAME, A.; SEKANINA, L. An Evolutionary-Based Algorithm to the Module Selection Problem with Resource Sharing in High-Level Synthesis. Advances in Nature-Inspired Computation: The PPSN VII Workshops. Reading: PEDAL, Department of Computer Science, University of Reading, 2002. p. 45-46. ISBN: 0-9543481-0-9. Detail
  • SLLAME, A.; SEKANINA, L. An Evolutionary-Based Algorithm to the Module Selection Process in High-Level Synthesis. Mendel 2002 - 8th International Conference on Soft Computing. Brno: Brno University of Technology, 2002. p. 87-92. ISBN: 80-214-2135-5. Detail
  • STRNADEL, J.; KOTÁSEK, Z. Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. Proceedings of Euromicro Symposium on Digital System Design Architectures, Methods and Tools DSD'2002. Los Alamitos: IEEE Computer Society Press, 2002. p. 166-173. ISBN: 0-7695-1790-0. Detail
  • ZBOŘIL, F., KOTÁSEK, Z., MIKA, D., STRNADEL, J. The Identification of Feedback Loops in RTL Structures. In Proceedings of The fifth International Scientific Conference Electronic Computers and Informatics 2002. Edition 55. Košice: The University of Technology Košice, 2002. p. 142-147. ISBN: 80-7099-879-2. Detail

2001

  • DRÁBEK, V. Configurable Computing. Advanced Simulation of Systems. Ostrava: 2001. p. 59-63. ISBN: 80-85988-61-5. Detail
  • KOTÁSEK, Z., STRNADEL, J. Analytic Approach to RTL Testability Analysis. In Proceedings of 7th Conference Student FEI 2001. Brno: Brno University of Technology, 2001. p. 363 ( p.)ISBN: 80-214-1860-5. Detail
  • KOTÁSEK, Z.; RŮŽIČKA, R.; STRNADEL, J. Formal and Analytical Approaches to the Testability Analysis - the Comparison. Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2001. Gyor: SZIF-UNIVERSITAS Ltd., Hungary, 2001. p. 123-128. ISBN: 963-7175-16-4. Detail
  • KOTÁSEK, Z.; RŮŽIČKA, R.; STRNADEL, J.; ZBOŘIL, F. Two Level Testability System. Proceedings of the 35th Spring International Conference MOSIS'01. Ostrava: 2001. p. 433-440. ISBN: 80-85988-57-7. Detail
  • KOTÁSEK, Z.; STRNADEL, J. RTL Testability Analysis Based on Genetic Algorithm Implementation. Proceedings of the IWCIT'01. Ostrava: Faculty of Electrical Engineering and Computer Science, VSB-TU Ostrava, 2001. p. 83-88. ISBN: 80-7078-907-7. Detail
  • KOTÁSEK, Z.; STRNADEL, J. RTL Testability Analysis Based on Genetic Algorithm Implementation. Proceedings of the Tenth ICNACSA. Plovdiv: unspecified agency, 2001. p. 89-89. Detail
  • KOTÁSEK, Z.; STRNADEL, J.; RŮŽIČKA, R.; HLAVIČKA, J. Interactive Tool for Behavioral Level Testability Analysis. Proceedings of the IEEE ETW 2001. Stockholm: 2001. p. 117-119. Detail
  • SLLAME, A.; DRÁBEK, V. Specification and Synthesis of Reusable Modules in VHDL. Proceedings of fourth International Wokshop on IEEE Design and Diagnostics of Electronic Circuits and Systems IEEE DDCSE01. Gyor, Hungary: SZIF-UNIVERSITAS Ltd., Hungary, 2001. p. 137-140. ISBN: 963-7175-16-4. Detail
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