Project Details

Metody návrhu aplikací založených na vyvíjejících se obvodech

Project Period: 1. 1. 2003 – 31. 12. 2005

Project Type: grant

Code: GP102/03/P004

Agency: Czech Science Foundation

Program: Postdoktorandské granty

English title
Evolvable hardware based applications design methods
Type
grant
Keywords

hardware; computational intelligence; evolvable hardware; design methodology

Abstract

The project deals with evolvable hardware, i.e. it combines evolutionary algorithms with reconfigurable hardware. Evolvable hardware enables to design high-performance and adaptive solutions for such applications in which the problem specification is unknown in the design time or can vary in time. The routine design of such applications is in fact impossible in Field Programmable Gate Arrays (FPGA) nowadays. The goal of the project is to introduce, develop, and test a methodology for evolvable hardware based application(s) design, which utilizes common FPGAs. In particular, a design system that will assist the designer during application design and which will enable to generate the description of application's software as well as hardware parts (e.g. as IP macros) will be developed. The methodology will be based on component approach to evolvable hardware and virtual reconfigurable devices introduced by the proposer. Adaptive embedded (e.g. multimedia) systems represent typical application domain of the project. A typical application will be designed using the proposed methodology.

Team members
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY) – research leader
Publications

2006

  • ZEBULUM, R.; KEYMEULEN, D.; RAMESHAM, R.; SEKANINA, L.; MAO, J.; KUMAR, N.; STOICA, A. Characterization and Synthesis of Circuits at Extreme Low Temperatures. In Evolvable Hardware. Genetic and Evolutionary Computation. Berlin: Springer Verlag, 2006. p. 161-172. ISBN: 0-387-24386-0. Detail

2005

  • BIDLO, M.; SEKANINA, L. Providing Information from the Environment for Growing Electronic Circuits Through Polymorphic Gates. Proc. of Genetic and Evolutionary Computation Conference - Workshops 2005. New York: Association for Computing Machinery, 2005. p. 242-248. ISBN: 1-59593-097-3. Detail
  • KOŘENEK, J.; SEKANINA, L. Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2005. p. 46-55. ISBN: 978-3-540-28736-0. Detail
  • MARTÍNEK, T.; SEKANINA, L. An Evolvable Image Filter: Experimental Evaluation of a Complete Hardware Implementation in FPGA. In Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2005. p. 76-85. ISBN: 978-3-540-28736-0. Detail
  • SEKANINA, L. Evolutionary Design of Gate-Level Polymorphic Digital Circuits. Applications of Evolutionary Computation. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2005. p. 185-194. ISBN: 978-3-540-25396-9. Detail
  • SEKANINA, L. Evoluční design poráží řešení vytvořená kreativním návrhářem. Vesmír, 2005, roč. 84, č. 1, s. 44-46. ISSN: 0042-4544. Detail
  • SEKANINA, L.; BIDLO, M. Evolutionary Design of Arbitrarily Large Sorting Networks Using Development. Genetic Programming and Evolvable Machines, 2005, vol. 6, no. 3, p. 319-347. ISSN: 1389-2576. Detail
  • SEKANINA, L.; ZEBULUM, R. Evolutionary discovering of the concept of the discrete state at the transistor level. Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2005. p. 73-78. ISBN: 0-7695-2399-4. Detail
  • ZEBULUM, R.; STOICA, A.; KEYMEULEN, D.; SEKANINA, L. Evolvable Hardware System at Extreme Low Temperatures. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2005. p. 37-45. ISBN: 978-3-540-28736-0. Detail

2004

  • DRÁBEK, V. Binární algebry a kódy aneb ten nádherný binární svět. I & IT'04 Informatika a informačné technológie 2004. Banská Bystrica: Univerzita Mateja Bela v Banskej Bystrici, 2004. s. 111-118. ISBN: 80-8083-017-7. Detail
  • FRIEDL, Š.; SEKANINA, L. The First Circuits Evolved in a Physical Virtual Reconfigurable Device. Proc. of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Bratislava: Slovak Academy of Science, 2004. p. 35-42. ISBN: 80-969117-9-1. Detail
  • SEKANINA, L. Evolutionary Design Space Exploration for Median Circuits. Lecture Notes in Computer Science, 2004, vol. 2004, no. 3005, p. 240-249. ISSN: 0302-9743. Detail
  • SEKANINA, L. Evolvable computing by means of evolvable components. Natural Computing, 2004, vol. 3, no. 3, p. 323-355. ISSN: 1567-7818. Detail
  • SEKANINA, L. Evolving Constructors for Infinitely Growing Sorting Networks and Medians. Lecture Notes in Computer Science, 2004, vol. 2004, no. 2932, p. 314-323. ISSN: 0302-9743. Detail
  • SEKANINA, L.; DRÁBEK, V. Theory and Applications of Evolvable Embedded Systems. Proc. of the 11th IEEE Int. Conference and Workshop on the Engineering of Computer-Based Systems. Los Alamitos, CA: IEEE Computer Society Press, 2004. p. 186-193. ISBN: 0-7695-2125-8. Detail
  • SEKANINA, L.; FRIEDL, Š. On Routine Implementation of Virtual Evolvable Devices Using COMBO6. Proc. of the 2004 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2004. p. 63-70. ISBN: 0-7695-2145-2. Detail
  • SEKANINA, L.; FRIEDL, Š. An Evolvable Combinational Unit for FPGAs. Computing and Informatics, 2004, vol. 23, no. 5, p. 461-486. ISSN: 1335-9150. Detail
  • TORRESEN, J.; BAKKE, J.; SEKANINA, L. Efficient Image Filtering and Information Reduction in Reconfigurable Logic. Proc. of 2004 Norchip conference. Oslo: IEEE Computer Society Press, 2004. p. 63-66. ISBN: 0-7803-8510-1. Detail
  • TORRESEN, J.; BAKKE, J.; SEKANINA, L. Efficient Recognition of Speed Limit Signs. Proc. of the 7th International IEEE Conference on Intelligent Transportation Systems. Los Alamos: IEEE Computer Society Press, 2004. p. 652-656. ISBN: 0-7803-8501-2. Detail
  • TORRESEN, J.; BAKKE, J.; SEKANINA, L. Recognizing Speed Limit Sign Numbers by Evolvable Hardware. Lecture Notes in Computer Science, 2004, vol. 2004, no. 3242, p. 682-691. ISSN: 0302-9743. Detail
  • VAŠÍČEK, Z.; SEKANINA, L. Evoluční návrh kombinačních obvodů. Elektrorevue - Internetový časopis (http://www.elektrorevue.cz), 2004, roč. 2004, č. 43, s. 1-6. ISSN: 1213-1539. Detail

2003

  • FRIEDL, Š.; SEKANINA, L. Evoluční algoritmus ve VHDL - jádro jednoduchého genetického systému (technická zpráva EVA2003). Brno: 2003. s. 0-0. Detail
  • SEKANINA, L. Evolvable Components - From Theory to Hardware Implementations. Natural Computing Series. Natural Computing Series. Berlin: Springer Verlag, 2003. 194 p. ISBN: 3-540-40377-9. Detail
  • SEKANINA, L. Towards Evolvable IP Cores for FPGAs. Proc. of The 2003 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2003. p. 145-154. ISBN: 0-7695-1977-6. Detail
  • SEKANINA, L. From Implementations to a General Concept of Evolvable Machines. Lecture Notes in Computer Science, 2003, vol. 2003, no. 2610, p. 424-433. ISSN: 0302-9743. Detail
  • SEKANINA, L. Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware. Lecture Notes in Computer Science, 2003, vol. 2003, no. 2606, p. 186-197. ISSN: 0302-9743. Detail
  • SEKANINA, L.; RŮŽIČKA, R. Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers. The 2003 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2003. p. 135-144. ISBN: 0-7695-1977-6. Detail
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