Project Details

Matematické a inženýrské metody pro vývoj spolehlivých a bezpečných paralelních a distribuovaných počítačových systémů

Project Period: 30. 1. 2009 – 31. 12. 2012

Project Type: grant

Code: GD102/09/H042

Agency: Czech Science Foundation

Program: Doktorské granty

English title
Mathematical and Engineering Approaches to Developing Reliable and Secure Concurrent and Distributed Computer Systems
Type
grant
Keywords

preparation of selected PhD students, reliability and security, concurrent and distributed systems, mathematical and engineering approaches

Abstract

The basic aim of the
project is to create an exceptional program for educating excellent
PhD students from FIT BUT and FI MU within research targeted at
solving current scientific problems of reliability and security of
concurrent and distributed systems, which is one of the key issues of
the contemporary computer science. Within this framework, the project
covers a wide variety of concrete problems ranging from the design of
reliable computing platforms, through the area of computer security
to methods of automatic verification of computer systems. The
complexity of the studied problems necessitates a use of a
combination of exact mathematical approaches with heuristic
engineering techniques, which is ensured in the project by a unique
combination of researchers with theoretical as well as engineering
backgrounds. Apart from the complex and interdisciplinary approach,
another key aspect of the preparation of students in the project lies
in their intense involvement in international activities, based on
exceptional international relations of the project leaders.

Team members
Češka Milan, prof. RNDr., CSc. – research leader
Bartoš Václav, Ing., Ph.D.
Bouda Jan, RNDr., Ph.D.
Brim Luboš, doc. RNDr., CSc. (CM-SFE)
Černá Ivana, prof. RNDr., CSc. (CM-SFE)
Dolíhal Luděk, Ing., Ph.D.
Drahošová Michaela, Ing., Ph.D. (DCSY)
Dudka Vendula, Ing.
Dvořák Václav, prof. Ing., DrSc.
Gruska Jozef, prof. RNDr., DrSc.
Hanáček Petr, doc. Dr. Ing. (DITS)
Holík Lukáš, doc. Mgr., Ph.D. (DITS)
Holub Petr (FIT)
Hruška Tomáš, prof. Ing., CSc. (DIFS)
Husár Adam, Ing., Ph.D.
Jurnečka Peter, Ing., Ph.D.
Kolář Dušan, doc. Dr. Ing. (DIFS)
Konečný Filip, Ing., Ph.D.
Korček Pavol, Ing., Ph.D. (DCSY)
Kotásek Zdeněk, doc. Ing., CSc.
Koutný Jiří, Ing., Ph.D.
Křena Bohuslav, Ing., Ph.D. (DITS)
Křetínský Mojmír, prof. RNDr., CSc. (CM-SFE)
Lengál Ondřej, Ing., Ph.D. (DITS)
Letko Zdeněk, Ing., Ph.D. (CM-SFE)
Matyáš Václav, Dr. (CM-SFE)
Matyska Luděk
Mikušek Petr, Ing.
Pospíchal Petr, Ing.
Přikryl Zdeněk, Ing., Ph.D.
Samek Jan, Ing., Ph.D. (CM-SFE)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Straka Martin, Ing., Ph.D.
Šimáček Jiří, Ing., Ph.D.
Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Vojnar Tomáš, prof. Ing., Ph.D. (DITS)
Zachariášová Marcela, Ing., Ph.D. (DCSY)
Publications

2013

  • LETKO, Z. Analysis and Testing of Concurrent Programs. Information Sciences and Technologies Bulletin of the ACM Slovakia, 2013, vol. 5, no. 3, p. 1-8. ISSN: 1338-1237. Detail
  • STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z.; MIČULKA, L. Fault Tolerant System Design and SEU Injection Based Testing. Microprocessors and Microsystems, 2013, vol. 2013, no. 37, p. 155-173. ISSN: 0141-9331. Detail

2012

  • BARTOŠ, P.; KOTÁSEK, Z. Reduction of Test Vectors Number based on Parasitic Capacity Extraction of Scan Chain Wires. Brno: 2012. s. 1 (1 s.). Detail
  • BARTOŠ, P.; KOTÁSEK, Z. Reduction of Test Vectors Number based on Parasitic Capacity Extraction of Scan Chain Wires. Proceedings of CSE 2012 International Scientific Conference on Computer Science and Engineering. Košice: Faculty of Electrical Engineering and Informatics, University of Technology Košice, 2012. p. 162-169. ISBN: 978-80-8143-049-7. Detail
  • BIDLO, M.; VAŠÍČEK, Z. Evolution of Cellular Automata Using Instruction-Based Approach. In 2012 IEEE World Congress on Computational Intelligence. CA: Institute of Electrical and Electronics Engineers, 2012. p. 1060-1067. ISBN: 978-1-4673-1508-1. Detail
  • ČEŠKA, M.; FIEDOR, J.; GACH, M. A Novel Approach to Modechart Verification of Real-Time systems. Lecture Notes in Computer Science, 2012, vol. 2012, no. 6927, p. 559-567. ISSN: 0302-9743. Detail
  • DOLÍHAL, L.; HRUŠKA, T.; MASAŘÍK, K. Usage of simulators in testing system. Industrial Simulation Conference. Brno: EUROSIS, 2012. p. 74-78. ISBN: 978-90-77381-71-7. Detail
  • DOLÍHAL, L.; HRUŠKA, T.; MASAŘÍK, K. Testing of an automatically generated compiler, Review of retargetable testing system. International Journal on Advances in Software, 2012, vol. 2012, no. 1, p. 15-26. ISSN: 1942-2628. Detail
  • DRAHOŠOVÁ, M.; SEKANINA, L. Acceleration of Evolutionary Image Filter Design Using Coevolution in Cartesian GP. 8th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2012. p. 121-121. ISBN: 978-80-87342-15-2. Detail
  • DRAHOŠOVÁ, M.; SEKANINA, L. Acceleration of Evolutionary Image Filter Design Using Coevolution in Cartesian GP. Lecture Notes in Computer Science, 2012, vol. 2012, no. 7491, p. 163-172. ISSN: 0302-9743. Detail
  • DUDKA, V.; KŘENA, B.; LETKO, Z.; UR, S.; VOJNAR, T. Testing of Concurrent Programs with Genetic Algorithms. Lecture Notes in Computer Science, 2012, roč. 2012, č. 7515, s. 152-167. ISSN: 0302-9743. Detail
  • DUDKA, V.; KŘENA, B.; LETKO, Z.; VOJNAR, T. Testing of Concurrent Programs Using Genetic Algorithms. FIT-TR-2012-01, Brno: 2012. p. 0-0. Detail
  • FIEDOR, J.; KŘENA, B.; LETKO, Z.; VOJNAR, T. A Uniform Classification of Common Concurrency Errors. Lecture Notes in Computer Science, 2012, vol. 2012, no. 6927, p. 519-526. ISSN: 0302-9743. Detail
  • HOLÍK, L.; ROGALEWICZ, A.; ŠIMÁČEK, J.; VOJNAR, T.; HABERMEHL, P. Forest Automata for Verification of Heap Manipulation. FORMAL METHODS IN SYSTEM DESIGN, 2012, vol. 2012, no. 41, p. 83-106. ISSN: 0925-9856. Detail
  • IOSIF, R.; HOJJAT, H.; KONEČNÝ, F.; KUNCAK, V.; RUMMER, P. Accelerating Interpolants. Lecture Notes in Computer Science, 2012, vol. 2012, no. 7561, p. 187-202. ISSN: 0302-9743. Detail
  • JURNEČKA, P.; HANÁČEK, P.; KAČIC, M. Concept of parallel code generating and refactoring system for safety standards compliance. 2012. p. 0-0. Detail
  • JURNEČKA, P.; HENZL, M.; KAČIC, M.; HANÁČEK, P. Concept of parallel code refactoring system for safety standards compliance. 2012. s. 0-0. Detail
  • KONEČNÝ, F.; HOJJAT, H.; IOSIF, R.; KUNCAK, V.; RUMMER, P.; GARNIER, F. A Verification Toolkit for Numerical Transition Systems. Lecture Notes in Computer Science, 2012, vol. 2012, no. 7436, p. 247-251. ISSN: 0302-9743. Detail
  • KONEČNÝ, F.; IOSIF, R.; BOZGA, M. Deciding Conditional Termination. Lecture Notes in Computer Science, 2012, vol. 2012, no. 7214, p. 252-266. ISSN: 0302-9743. Detail
  • KORČEK, P.; SEKANINA, L.; FUČÍK, O. Calibration of Traffic Simulation Models Using Vehicle Travel Times. Lecture Notes in Computer Science, 2012, vol. 2012, no. 7495, p. 807-816. ISSN: 0302-9743. Detail
  • KORČEK, P.; SEKANINA, L.; FUČÍK, O. Evolutionary approach to calibration of cellular automaton based traffic simulation model. In Proceedings of the 15th International IEEE Conference on Intelligent Transportation Systems. Anchorage: IEEE Intelligent Transportation Systems Society, 2012. p. 122-129. ISBN: 978-1-4673-3062-6. Detail
  • KOTÁSEK, Z.; BOUDA, J.; ČERNÁ, I.; SEKANINA, L.; VOJNAR, T.; ANTOŠ, D. Mathematical and Engineering Methods in Computer Science, 7th International Doctoral Workshop, Revised Selected Papers. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2012. p. 0-0. ISBN: 978-3-642-25928-9. Detail
  • KOUTNÝ, J. On Path-Controlled Grammars and Pseudoknots. Proceedings of the 18th Conference STUDENT EEICT 2012 Volume 3. Brno: Brno University of Technology, 2012. p. 391-395. ISBN: 978-80-214-4462-1. Detail
  • KOUTNÝ, J.; MEDUNA, A. Tree-Controlled Grammars with Restrictions Placed upon Cuts and Paths. Kybernetika, 2012, vol. 48, no. 1, p. 165-175. ISSN: 0023-5954. Detail
  • KŘENA, B.; LETKO, Z.; VOJNAR, T. Analysis and Testing of Concurrent Programs. FIT Monograph. FIT Monograph. Brno: Faculty of Information Technology BUT, 2012. 136 p. ISBN: 978-80-214-4464-5. Detail
  • KŘENA, B.; LETKO, Z.; VOJNAR, T. Noise Injection Heuristics for Concurrency Testing. Lecture Notes in Computer Science, 2012, vol. 2012, no. 7119, p. 123-131. ISSN: 0302-9743. Detail
  • LENGÁL, O.; ŠIMÁČEK, J.; VOJNAR, T. VATA: A Library for Efficient Manipulation of Non-Deterministic Tree Automata. Lecture Notes in Computer Science, 2012, vol. 2012, no. 7214, p. 79-94. ISSN: 0302-9743. Detail
  • LETKO, Z.; VOJNAR, T.; KŘENA, B. Coverage Metrics for Saturation-based and Search-based Testing of Concurrent Software. Lecture Notes in Computer Science, 2012, roč. 2012, č. 7186, s. 177-192. ISSN: 0302-9743. Detail
  • MALAČKA, O.; SAMEK, J.; ZBOŘIL, F.; ZBOŘIL, F. Decision Making and Recommendation Protocol Based on Trust for Multi-agent Systems. Lecture Notes in Computer Science, 2012, vol. 2012, no. 7138, p. 280-291. ISSN: 0302-9743. Detail
  • SAMEK, J. Multi-contextual Trust Model for Multi-Agent Systems. Information Sciences and Technologies Bulletin of the ACM Slovakia, 2012, vol. 4, no. 1, p. 44-54. ISSN: 1338-1237. Detail
  • STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. FPGA-based Fault Tolerant Architectures and Their Dependability Analysis. MEMICS'12 -- 8th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Faculty of Informatics MU, 2012. p. 1 (1 s.). Detail
  • ZACHARIÁŠOVÁ, M. Acceleration of Functional Verification in the Development Cycle of Hardware Systems. Počítačové architektury a diagnostika. Praha: Czech Technical University, 2012. p. 73-78. ISBN: 978-80-01-05106-1. Detail
  • ZACHARIÁŠOVÁ, M.; LENGÁL, O. Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures. FIT-TR-2012-03, Brno: Faculty of Information Technology BUT, 2012. p. 0-0. Detail
  • ZACHARIÁŠOVÁ, M.; LENGÁL, O. Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures. Lecture Notes in Computer Science, 2012, vol. 2013, no. 7857, p. 266-273. ISSN: 0302-9743. Detail

2011

  • ABDULLA, P.; CHEN, Y.; CLEMENTE, L.; HOLÍK, L.; HONG, C.; MAYR, R.; VOJNAR, T. Advanced Ramsey-based Büchi Automata Inclusion Testing. FIT-TR-2011-03, Brno: Faculty of Information Technology BUT, 2011. p. 0-0. Detail
  • ABDULLA, P.; CHEN, Y.; CLEMENTE, L.; HOLÍK, L.; HONG, C.; MAYR, R.; VOJNAR, T. Advanced Ramsey-based Büchi Automata Inclusion Testing. Lecture Notes in Computer Science, 2011, vol. 2011, no. 6901, p. 187-202. ISSN: 0302-9743. Detail
  • BARTOŠ, P. Metody optimalizace propojení scan řetězce. Počítačové architektury a diagnostika 2011. Bratislava: Vydavateľstvo STU, 2011. s. 97-102. ISBN: 978-80-227-3552-0. Detail
  • BARTOŠ, P. Test Time Reduction by Scan Chain Reordering. Proceedings of the 17th Conference STUDENT EEICT 2011. Volume 3. Brno: Faculty of Electrical Engineering and Communication BUT, 2011. p. 564-568. ISBN: 978-80-214-4273-3. Detail
  • BARTOŠ, P.; KOTÁSEK, Z.; DOHNAL, J. Decreasing Test Time by Scan Chain Reorganization. 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Brno University of Technology, 2011. p. 108-108. ISBN: 978-80-214-4305-1. Detail
  • BARTOŠ, P.; KOTÁSEK, Z.; DOHNAL, J. Decreasing Test Time by Scan Chain Reorganization. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011. p. 371-374. ISBN: 978-1-4244-9753-9. Detail
  • ČERMÁK, M.; KOUTNÝ, J.; MEDUNA, A. Parsing Based on n-Path Tree-Controlled Grammars. Theoretical and Applied Informatics, 2011, vol. 23, no. 3, p. 213-228. ISSN: 1896-5334. Detail
  • DOLÍHAL, L.; HRUŠKA, T. Porting of C library, Testing of generated compiler. InfoWare 2011. Luxembourg: International Academy, Research, and Industry Association, 2011. p. 125-130. ISBN: 978-1-61208-008-6. Detail
  • DUDKA, K.; PERINGER, P.; VOJNAR, T. An Easy to Use Infrastructure for Building Static Analysis Tools. Proceedings of the 13th International Conference on Computer Aided Systems Theory. Universidad de Las Palmas de Canaria: The Universidad de Las Palmas de Gran Canaria, 2011. p. 328-329. ISBN: 978-84-693-9560-8. Detail
  • DVOŘÁK, V.; JAROŠ, J. A Programmable Interconnection Network for Multiple Communication Patterns. Proceedings of the Sixth International Conference on Systems, ICONS 2011. St. Maarten: International Academy, Research, and Industry Association, 2011. p. 6-11. ISBN: 978-1-61208-002-4. Detail
  • FIEDOR, J.; GACH, M.; ČEŠKA, M. A Novel Approach to Modechart Verification of Real-Time Systems. Proceedings of the 13th International Conference on Computer Aided Systems Theory. Universidad de Las Palmas de Canaria: The Universidad de Las Palmas de Gran Canaria, 2011. p. 338-339. ISBN: 978-84-693-9560-8. Detail
  • FIEDOR, J.; LETKO, Z.; VOJNAR, T.; KŘENA, B. A Uniform Classification of Common Concurrency Errors. Proceedings of the 13th International Conference on Computer Aided Systems Theory. Universidad de Las Palmas de Canaria: The Universidad de Las Palmas de Gran Canaria, 2011. p. 326-327. ISBN: 978-84-693-9560-8. Detail
  • HANÁČEK, P.; JURNEČKA, P. Využitie grafických kariet na útoky silou. DSM Data Security Management, 2011, roč. 15, č. 2, s. 10-13. ISSN: 1211-8737. Detail
  • HOLÍK, L.; LENGÁL, O.; ŠIMÁČEK, J.; VOJNAR, T. Efficient Inclusion Checking on Explicit and Semi-Symbolic Tree Automata. FIT-TR-2011-04, Brno: Faculty of Information Technology BUT, 2011. p. 0-0. Detail
  • HOLÍK, L.; LENGÁL, O.; ŠIMÁČEK, J.; VOJNAR, T. Efficient Inclusion Checking on Explicit and Semi-Symbolic Tree Automata. Lecture Notes in Computer Science, 2011, vol. 2011, no. 6996, p. 243-258. ISSN: 0302-9743. Detail
  • HOLÍK, L.; ROGALEWICZ, A.; ŠIMÁČEK, J.; VOJNAR, T.; HABERMEHL, P. Forest Automata for Verification of Heap Manipulation. FIT-TR-2011-01, Brno: Faculty of Information Technology BUT, 2011. p. 0-0. Detail
  • HOLÍK, L.; ROGALEWICZ, A.; ŠIMÁČEK, J.; VOJNAR, T.; HABERMEHL, P. Forest Automata for Verification of Heap Manipulation. Lecture Notes in Computer Science, 2011, vol. 2011, no. 6806, p. 424-440. ISSN: 0302-9743. Detail
  • JURNEČKA, P.; HENZL, M.; KAČIC, M.; HANÁČEK, P. Concept of parallel code refactoring system for safety standards compliance. 2011. p. 0-0. Detail
  • KORČEK, P. Simulácie dopravy pre dlhodobú predpoveď stavu dopravy. Počítačové architektury a diagnostika 2011. Bratislava: Faculty of Informatics and Information Technology Slovak University of Technology in Bratislava, 2011. s. 115-120. ISBN: 978-80-227-3552-0. Detail
  • KORČEK, P.; SEKANINA, L.; FUČÍK, O. A Scalable Cellular Automata Based Microscopic Traffic Simulation. 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2011. p. 1 (1 s.). ISBN: 978-80-214-4305-1. Detail
  • KORČEK, P.; SEKANINA, L.; FUČÍK, O. A Scalable Cellular Automata Based Microscopic Traffic Simulation. Proceedings of the IEEE Intelligent Vehicles Symposium 2011 (IV11). Baden-Baden: IEEE Intelligent Transportation Systems Society, 2011. p. 13-18. ISBN: 978-1-4577-0889-3. Detail
  • KORČEK, P.; SEKANINA, L.; FUČÍK, O. Cellular automata based traffic simulation accelerated on GPU. Proceedings of the 17th International Conference on Soft Computing (MENDEL2011). Brno: Institute of Automation and Computer Science FME BUT, 2011. p. 395-402. ISBN: 978-80-214-4302-0. Detail
  • KORČEK, P.; SEKANINA, L.; FUČÍK, O. Microscopic traffic simulation using CUDA. Advanced Computer Architecture and Compilation for High-Performace and Embedded Systems (ACACES 2011) Poster Abstracts. Fiuggi: Academia Press, 2011. p. 207-210. ISBN: 978-90-382-1798-7. Detail
  • KOUTNÝ, J.; KŘIVKA, Z.; MEDUNA, A. Pumping Properties of Path-Restricted Tree-Controlled Languages. 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Brno University of Technology, 2011. p. 61-69. ISBN: 978-80-214-4305-1. Detail
  • MALAČKA, O.; SAMEK, J.; ZBOŘIL, F.; ZBOŘIL, F. Decision Making and Recommendation Protocol Based on Trust for Multi-Agent Systems. Proceedings of Trust, Reputation and User Modeling Workshop (TRUM 2011). Girona: 2011. p. 33-40. Detail
  • MATOUŠEK, J.; KORČEK, P. Precise IPv4/IPv6 Packet Generator Based on NetCOPE Platform. In Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011. Cottbus: IEEE Computer Society, 2011. p. 319-324. ISBN: 978-1-4244-9756-0. Detail
  • MIKUŠEK, P.; TOMEC, M.; DVOŘÁK, V. A Cascade Decomposition of Application-Specific Systems. MEMICS Proc. Brno: Brno University of Technology, 2011. p. 78-85. ISBN: 978-80-214-4305-1. Detail
  • PŘIKRYL, Z. Advanced Methods of Microprocessor Simulation. Information Sciences and Technologies Bulletin of the ACM Slovakia, 2011, vol. 3, no. 3, p. 1-13. ISSN: 1338-1237. Detail
  • PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D. Fast Just-In-Time Translated Simulation for ASIP Design. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Cottbus: IEEE Computer Society, 2011. p. 279-282. ISBN: 978-1-4244-9753-9. Detail
  • PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D. Fast Translated Simulation of ASIPs. OpenAccess Series in Informatics (OASIcs), 2011, vol. 16, no. 1, p. 93-100. ISSN: 2190-6807. Detail
  • PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D.; MASAŘÍK, K.; HUSÁR, A. Design and Simulation of High Performance Parallel Architectures Using the ISAC Language. GSTF International Journal on Computing, 2011, vol. 1, no. 2, p. 97-106. ISSN: 2010-2283. Detail
  • SAMEK, J.; MALAČKA, O.; ZBOŘIL, F.; HANÁČEK, P. Multi-Agent Experimental Framework with Hierarchical Model of Trust in Contexts for Decision Making. Proceeding of the 2nd International Conference on Computer Modelling and Simulation. Brno: Department of Intelligent Systems FIT BUT, 2011. p. 128-136. ISBN: 978-80-214-4320-4. Detail
  • VAŠÍČEK, Z.; BIDLO, M. Evolutionary Design of Robust Noise-Specific Image Filters. In 2011 IEEE Congress on Evolutionary Computation. New Orleans: IEEE Computer Society, 2011. p. 269-276. ISBN: 978-1-4244-7834-7. Detail
  • VAŠÍČEK, Z.; BIDLO, M.; SEKANINA, L.; GLETTE, K. Evolutionary Design of Efficient and Robust Switching Image Filters. In Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2011. p. 192-199. ISBN: 978-1-4577-0599-1. Detail
  • VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Optimization of Complex Digital Circuits. 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2011. p. 127-127. ISBN: 978-80-214-4305-1. Detail
  • VAŠÍČEK, Z.; SEKANINA, L. Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. Genetic Programming and Evolvable Machines, 2011, vol. 12, no. 3, p. 305-327. ISSN: 1389-2576. Detail
  • ZEMČÍK, P.; PŘIBYL, B.; ŽÁDNÍK, M.; KORČEK, P. Fast and Energy Efficient Image Processing Algorithms using FPGA. Proceedings of the 21th Conference on Field Programmable Logic and Applications Workshop. Chania: Institute of Electrical and Electronics Engineers, 2011. p. 35-36. ISBN: 978-0-7695-4529-5. Detail

2010

  • BIDLO, M.; VAŠÍČEK, Z.; SLANÝ, K. Sorting Network Development Using Cellular Automata. In Evolvable Systems: From Biology to Hardware. 9th International Conference, ICES 2010, York, UK, September 6-8, 2010, Proceedings, LNCS 6274. London: Springer London, 2010. p. 85-96. ISBN: 978-3-642-15322-8. Detail
  • BOZGA, M.; IOSIF, R.; KONEČNÝ, F. Fast Acceleration of Ultimately Periodic Relations. Computer Aided Verification. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2010. p. 227-242. ISBN: 978-3-642-14294-9. Detail
  • DVOŘÁK, V.; MIKUŠEK, P. Design of Arbiters and Allocators Based on Multi-Terminal BDDs. Journal of Universal Computer Science, 2010, vol. 16, no. 14, p. 1826-1852. ISSN: 0948-6968. Detail
  • FIEDOR, J.; KŘENA, B.; LETKO, Z.; VOJNAR, T. A Uniform Classification of Common Concurrency Errors. FIT-TR-2010-03, Brno: 2010. p. 0-0. Detail
  • HOLÍK, L.; ŠIMÁČEK, J. Optimizing an LTS-Simulation Algorithm. Computing and Informatics, 2010, vol. 2010, no. 7, p. 1337-1348. ISSN: 1335-9150. Detail
  • HOLÍK, L.; VOJNAR, T.; ABDULLA, P.; CHEN, Y.; MAYR, R. When Simulation Meets Antichains (On Checking Language Inclusion of Nondeterministic Finite (Tree) Automata). FIT-TR-2010-01, Brno: Faculty of Information Technology BUT, 2010. p. 0-0. Detail
  • HOLÍK, L.; VOJNAR, T.; ABDULLA, P.; CHEN, Y.; MAYR, R. When Simulation Meets Antichains (On Checking Language Inclusion of Nondeterministic Finite (Tree) Automata). Tools and Algorithms for the Construction and Analysis of Systems. Lecture Notes in Computer Science. Berlín: Springer Verlag, 2010. p. 158-174. ISBN: 978-3-642-12001-5. Detail
  • HOLÍK, L.; VOJNAR, T.; CHEN, Y.; MAYR, R.; HONG, C.; ABDULLA, P.; CLEMENTE, L. Simulation Subsumption in Ramsey-Based Büchi Automata Universality and Inclusion Testing. Computer Aided Verification. Lecture Notes in Computer Science. Berlín: Springer Verlag, 2010. p. 132-147. ISBN: 978-3-642-14294-9. Detail
  • HOLÍK, L.; VOJNAR, T.; CHEN, Y.; MAYR, R.; HONG, C.; ABDULLA, P.; CLEMENTE, L. Simulation Subsumption in Ramsey-based Büchi Automata Universality and Inclusion Testing. FIT-TR-2010-02, Brno: Faculty of Information Technology BUT, 2010. p. 0-0. Detail
  • HUSÁR, A.; HRUŠKA, T.; MASAŘÍK, K.; PŘIKRYL, Z. Instruction Pipeline Modeling using Petri Nets. Proceedings of the International Workshop on Petri Nets and Software Engineering - PNSE'10. Proceedings of the International Workshop on Petri Nets and Software. Universität Hamburg: Technical Universityt Hamburg-Harburg, 2010. p. 163-164. ISBN: 978-972-8692-55-1. Detail
  • HUSÁR, A.; HRUŠKA, T.; TRMAČ, M.; PŘIKRYL, Z. Instruction Selection Patterns Extraction from Architecture Specification Language ISAC. Proceedings of the 16th Conference Student EEICT 2010 Volume 5. Brno: Faculty of Information Technology BUT, 2010. p. 166-170. ISBN: 978-80-214-4080-7. Detail
  • HUSÁR, A.; TRMAČ, M.; HRANÁČ, J.; HRUŠKA, T.; MASAŘÍK, K.; KOLÁŘ, D.; PŘIKRYL, Z. Automatic C Compiler Generation from Architecture Description Language ISAC. 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2010. p. 84-91. ISBN: 978-80-87342-10-7. Detail
  • KOTÁSEK, Z.; ŠKARVADA, J.; STRNADEL, J. Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences. Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010. p. 364-369. ISBN: 978-1-4244-6610-8. Detail
  • KŘENA, B.; LETKO, Z.; UR, S.; VOJNAR, T. A Platform for Search-Based Testing of Concurrent Software. PADTAD '10. Proceedings of the 8th Workshop on Parallel and Distributed Systems. Trento: Association for Computing Machinery, 2010. p. 48-58. ISBN: 978-1-60558-823-0. Detail
  • KŘENA, B.; LETKO, Z.; VOJNAR, T.; UR, S. A Platform for Search-Based Testing of Concurrent Software. 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2010. p. 208-208. ISBN: 978-80-87342-10-7. Detail
  • LETKO, Z. Sophisticated Testing of Concurrent Software. SSBSE '10. Proceedings of 2nd International Symposium on Search Based Software Engineering. Benevento: Institute of Electrical and Electronics Engineers, 2010. p. 36-40. ISBN: 978-0-7695-4195-2. Detail
  • MALAČKA, O.; ZBOŘIL, F.; SAMEK, J. Increasing Profit in Agent Business Model with Trust. Proceedings of the 7th EUROSIM Congress on Modelling and Simulation. Vol. 2. Praha: Czech Technical University Publishing House, 2010. p. 109-114. ISBN: 978-80-01-04589-3. Detail
  • PŘIKRYL, Z.; HRUŠKA, T.; MASAŘÍK, K.; HUSÁR, A. Fast Cycle-Accurate Compiled Simulation. 10th IFAC Workshop on Programmable Devices and Embedded Systems, PDeS 2010. Programmable devices and systems. Pszczyna: IFAC, 2010. p. 97-102. ISBN: 978-3-902661-95-1. ISSN: 1474-6670. Detail
  • PŘIKRYL, Z.; HUSÁR, A.; HRUŠKA, T.; MASAŘÍK, K. ASIP Design in the Lissom Project. ACACES 2010 - Poster Abstracts. Ghent: High Performance and Embedded Architecture and Compilation, 2010. p. 105-108. ISBN: 978-90-382-1631-7. Detail
  • PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D. Fast Translated Simulation of ASIPs. 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2010. p. 135-142. ISBN: 978-80-87342-10-7. Detail
  • PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D.; MASAŘÍK, K.; HUSÁR, A. Design and Debugging of Parallel Architectures Using the ISAC Language. Proceedings ot the Annual International Conference on Advanced Distributed and Parallel Computing and Real-Time and Embedded Systems. Singapore: Global Science & Technology Forum, 2010. p. 213-221. ISBN: 978-981-08-7656-2. Detail
  • PŘIKRYL, Z.; MASAŘÍK, K.; HRUŠKA, T.; HUSÁR, A. Generated Cycle-Accurate Profiler for C Language. 13th EUROMICRO Conference on Digital System Design, DSD'2010. Lille: IEEE Computer Society, 2010. p. 263-268. ISBN: 978-0-7695-4171-6. Detail
  • SAMEK, J.; ZBOŘIL, F. Algorithmic Evaluation of Trust in Multilevel Model. Proceedings of the 7th EUROSIM Congress on Modelling and Simulation. Vol. 2. Praha: Czech Technical University Publishing House, 2010. p. 90-95. ISBN: 978-80-01-04589-3. Detail
  • SAMEK, J.; ZBOŘIL, F. ContextGraph: Simulation Tool for Hierarchical Model of Trust in Context. Proceedings of CSE 2010 International Scientific Conference on Computer Science and Engineering. Vol. 1. Košice: The University of Technology Košice, 2010. p. 265-270. ISBN: 978-80-8086-164-3. Detail
  • SAMEK, J.; ZBOŘIL, F. Hierarchical Model of Trust in Contexts. Networked Digital Technologies. Communications in Computer and Information Science. Communications in Computer and Information Science (CCIS). Heidelberg: Springer Verlag, 2010. p. 356-365. ISBN: 978-3-642-14305-2. ISSN: 1865-0929. Detail
  • SAMEK, J.; ZBOŘIL, F.; MALAČKA, O. Event Driven Multi-context Trust Model. Proceedings of the 10th International Conference on Intelligent Systems Design and Applications. Cairo: IEEE Computer Society, 2010. p. 911-917. ISBN: 978-1-4244-8135-4. Detail
  • ŠIMÁČEK, J.; SEKANINA, L.; STAREČEK, L. Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2010. p. 214-225. ISBN: 978-3-642-15322-8. Detail
  • STRAKA, M. Metodika pro návrh číslicových systémů se zvýšenou spolehlivostí v obvodech FPGA. Počítačové architektury a diagnostika 2010. Brno: Fakulta informačních technologií VUT v Brně, 2010. s. 159-164. ISBN: 978-80-214-4140-8. Detail
  • STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration. 13th EUROMICRO Conference on Digital System Design, DSD'2010. Lille: IEEE Computer Society, 2010. p. 365-372. ISBN: 978-0-7695-4171-6. Detail
  • STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA. NORCHIP 2010. Tampere: IEEE Computer Society, 2010. p. 1-4. ISBN: 978-1-4244-8971-8. Detail
  • STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Methodology for Design of Highly Dependable Systems in FPGA. International Scientific Conference on Computer Science and Engineering. Košice: The University of Technology Košice, 2010. p. 186-193. ISBN: 978-80-8086-164-3. Detail
  • STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs. Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Wien: IEEE Computer Society, 2010. p. 173-176. ISBN: 978-1-4244-6610-8. Detail
  • VAŠÍČEK, Z. Využití a akcelerace evolučních technik pro návrh číslicových obvodů. Počítačové architektury a diagnostika 2010. Brno: Fakulta informačních technologií VUT v Brně, 2010. s. 165-170. ISBN: 978-80-214-4140-8. Detail
  • VAŠÍČEK, Z.; SEKANINA, L. Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units. Computing and Informatics, 2010, vol. 29, no. 6, p. 1359-1371. ISSN: 1335-9150. Detail
  • VAŠÍČEK, Z.; SEKANINA, L.; BIDLO, M. A Method for Design of Impulse Bursts Noise Filters Optimized for FPGA Implementations. DATE 2010: Design, Automation and Test in Europe. Dresden: European Design and Automation Association, 2010. p. 1731-1736. ISBN: 978-3-9810801-6-2. Detail

2009

  • ABDULLA, P.; HOLÍK, L.; CHEN, Y.; VOJNAR, T. Mediating for Reduction (On Minimizing Alternating Büchi Automata). Brno: Faculty of Information Technology BUT, 2009. p. 0-0. Detail
  • BIDLO, M.; VAŠÍČEK, Z. Comparison of the Uniform and Non-Uniform Cellular Automata-Based Approach to the Development of Combinational Circuits. Proceedings 2009 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2009. p. 423-430. ISBN: 978-0-7695-3714-6. Detail
  • BIDLO, M.; VAŠÍČEK, Z. Development of Combinational Circuits Using Non-Uniform Cellular Automata: Initial Results. Genetic and Evolutionary Computation. New York: Association for Computing Machinery, 2009. p. 1839-1840. ISBN: 978-1-60558-325-9. Detail
  • BIDLO, M.; VAŠÍČEK, Z. Investigating Gate-Level Evolutionary Development of Combinational Multipliers Using Enhanced Cellular Automata-Based Model. Proc. of 2009 IEEE Congress on Evolutionary Computation. NA: IEEE Computational Intelligence Society, 2009. p. 2241-2248. ISBN: 978-1-4244-2958-5. Detail
  • ČEŠKA, M.; HÝSEK, J.; JANOUŠEK, V. Model-Based Design and Verification of Reactive Systems. Lecture Notes in Computer Science, 2009, vol. 2009, no. 5717, p. 865-872. ISSN: 0302-9743. Detail
  • HOLÍK, L.; ŠIMÁČEK, J. Optimizing an LTS-Simulation Algorithm. 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Faculty of Informatics MU, 2009. p. 93-101. ISBN: 978-3-939897-15-6. Detail
  • HOLÍK, L.; ŠIMÁČEK, J. Optimizing an LTS-Simulation Algorithm. FIT-TR-2009-03, Brno: 2009. p. 0-0. Detail
  • HOLÍK, L.; VOJNAR, T.; ABDULLA, P.; BOUAJJANI, A.; KAATI, L. Composed Bisimulation for Tree Automata. International Journal of Foundations of Computer Science, 2009, vol. 20, no. 4, p. 685-700. ISSN: 0129-0541. Detail
  • HOLÍK, L.; VOJNAR, T.; ABDULLA, P.; CHEN, Y. Mediating for Reduction (On Minimizing Alternating Büchi Automata). FIT-TR-2009-02, Brno: 2009. p. 0-0. Detail
  • HOLÍK, L.; VOJNAR, T.; ABDULLA, P.; CHEN, Y. Mediating for Reduction (On Minimizing Alternating Büchi Automata). IARCS Annual Conference on Foundations of Software Technology and Theoretical Computer Science (2009). LIPIcs, sv. 4. Wadern: Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik, 2009. s. 1-12. ISBN: 978-3-939897-13-2. Detail
  • HOLÍK, L.; VOJNAR, T.; ABDULLA, P.; KAATI, L. A Uniform (Bi-)Simulation-Based Framework for Reducing Tree Automata. ELECTRONIC NOTES IN THEORETICAL COMPUTER SCIENCE, 2009, vol. 2009, no. 251, p. 27-48. ISSN: 1571-0661. Detail
  • HUSÁR, A.; PŘIKRYL, Z.; MASAŘÍK, K.; HRUŠKA, T. ASIP Design using Architecture Description Language ISAC. ACACES 2009 - Poster Abstracts. Ghent: High Performance and Embedded Architecture and Compilation, 2009. p. 137-139. ISBN: 978-90-382-1467-2. Detail
  • HÝSEK, J.; ČEŠKA, M.; JANOUŠEK, V. Model-Based Design and Verification of Reactive Systems. Computer Aided Systems Theory. Las Palmas de Gran Canaria: 2009. p. 295-296. ISBN: 978-84-691-8502-5. Detail
  • IOSIF, R.; KONEČNÝ, F.; VOJNAR, T.; HABERMEHL, P.; BOZGA, M. Automatic Verification of Integer Array Programs. Computer Aided Verification. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2009. p. 157-172. ISBN: 978-3-642-02657-7. Detail
  • IOSIF, R.; KONEČNÝ, F.; VOJNAR, T.; HABERMEHL, P.; BOZGA, M. Automatic Verification of Integer Array Programs. TR-2009-2, Grenoble: VERIMAG, 2009. p. 0-0. Detail
  • KOTÁSEK, Z.; STRAKA, M. The Design of On-line Checkers and Their Use in Verification and Testing. Acta Electrotechnica et Informatica, 2009, vol. 2009, no. 3, p. 8-15. ISSN: 1335-8243. Detail
  • MIKUŠEK, P. Dekompoziční techniky pro aplikačně specifické systémy. Počítačové architektury a diagnostika 2009. Zlín: Univerzita Tomáše Bati ve Zlíně, 2009. s. 118-123. ISBN: 978-80-7318-847-4. Detail
  • MIKUŠEK, P. Multi-Terminal BDD Synthesis and Applications. Proceedings 19th International Conference on Field Programmable Logic and Applications (FPL). Prague: IEEE Computer Society, 2009. p. 721-722. ISBN: 978-1-4244-3892-1. Detail
  • MIKUŠEK, P.; DVOŘÁK, V. Heuristic Synthesis of MTBDDs Based On Local Width Minimization. 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2009. p. 235-235. ISBN: 978-80-87342-04-6. Detail
  • MIKUŠEK, P.; DVOŘÁK, V. Heuristic Synthesis of Multi-Terminal BDDs Based on Local Width/Cost Minimization. 12th EUROMICRO Conference on Digital System Design DSD 2009. Patras: IEEE Computer Society, 2009. p. 605-608. ISBN: 978-0-7695-3782-5. Detail
  • PŘIKRYL, Z.; HRUŠKA, T. Cycle Accurate Profiler for ASIPs. 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2009. p. 168-175. ISBN: 978-80-87342-04-6. Detail
  • PŘIKRYL, Z.; MASAŘÍK, K.; HRUŠKA, T.; HUSÁR, A. Fast Cycle-Accurate Interpreted Simulation. Tenth International Workshop on Microprocessor Test and Verification: Common Challenges and Solutions. Austin: IEEE Computer Society Press, 2009. p. 9-14. ISBN: 978-0-7695-4000-9. Detail
  • SAMEK, J.; ZBOŘIL, F. Agent Reasoning Based On Trust And Reputation. Proceedings MATHMOD 09 Vienna - Full Papers CD Volume. Vienna: ARGE Simulation News, 2009. p. 538-544. ISBN: 978-3-901608-35-3. Detail
  • STRAKA, M. Metodologie návrhu obvodů se zvýšenou spolehlivostí založených na FPGA. Počítačové architektury a diagnostika 2009. Zlin: Univerzita Tomáše Bati ve Zlíně, 2009. s. 141-146. ISBN: 978-80-7318-847-4. Detail
  • STRAKA, M.; KOTÁSEK, Z. High Availability Fault Tolerant Architectures Implemented into FPGAs. 12th EUROMICRO Conference on Digital System Design DSD 2009. Patras: IEEE Computer Society, 2009. p. 108-116. ISBN: 978-0-7695-3782-5. Detail
  • STRAKA, M.; KOTÁSEK, Z. Reliability Models for Fault Tolerant Architectures Based on FPGA. 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Faculty of Informatics MU, 2009. p. 239-239. ISBN: 978-80-87342-04-6. Detail
  • VAŠÍČEK, Z.; BIDLO, M.; SEKANINA, L.; TORRESEN, J.; GLETTE, K.; FURUHOLMEN, M. Evolution of Impulse Bursts Noise Filters. Proc. of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2009. p. 27-34. ISBN: 978-0-7695-3714-6. Detail
  • VAŠÍČEK, Z.; SEKANINA, L. Efficient Hardware Accelerator for Symbolic Regression Problems. 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2009. p. 192-199. ISBN: 978-80-87342-04-6. Detail
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