Evoluční návrh testovacích obvodů

Evolutionary Design of Benchmark Circuits

grant

benchmark circuits, evolutionary design, evolutionary programming

The project deals with develop a method for generation of synthetic benchmark circuits on register transfer level. In the project, the new approach, which utilizes evolutionary techniques for design a benchmark circuits with predefined structure and diagnostic properties (in terms of controllability and observability) is presented. Graph representation of the circuit is used for generation of benchmark circuits and circuit structure analysis. Testability analysis is performed by testability analysis tool developed on FIT BUT. The output of developed tool is in form of circuit described in synthesisable VHDL code.

Pečenka Tomáš, Ing., Ph.D. – research leader
Kotásek Zdeněk, doc. Ing., CSc.