Hardware Accelerator for Evolutionary Image Filters Design

Obvodový akcelerátor pro evoluční návrh obrazových filtrů

functional specimen

Use of the result by another entity is possible without acquiring a license (the result is not licensed)

The licensor does not require a license fee for the result in some cases

Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)

accelerator, FPGA, Combo6X, evolutionary algorithm, image filter

The EHWFILTER accelerator was developed in order to accelerate image filter evolution in hardware. It can automatically create a filter (e.g., to suppress shot noise) when noised image and uncorrupted original image are provided. The accelerator is implemented on the COMBO6X card equipped with Virtex II Pro 2VP50ff1517 FPGA. It consists of genetic unit, fitness unit and the so-called virtual reconfigurable circuit (VRC) which is utilized to evaluate candidate filters. Every image filter is considered as a digital circuit of nine 8-bit inputs and a single 8-bit output, which processes grayscale (8-bits/pixel) images. Training images are stored in external SRAM memories. The search algorithm is based on Cartesian Genetic Programming operating over 4x8 programmable elements, population size of 8 individuals, and 1 mutation/chromosome. This setting is default but can be changed. The accelerator is connected with PC using PCI bus. The system requires approx. 10 sec to produce a filter which is 44 times faster than the same algorithm running at the Celeron 2.4 GHz. 

Ústav počítačových systémů, Fakulta informačních technologií VUT v Brně, Božetěchova 2, 612 66 Brno, http://www.fit.vutbr.cz/units/UPSY/

Design and hardware implementation of a patent-invention machine, GACR, Standardní projekty, GA102/07/0850, 2007-2009, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, 2007-2013, running

Evolvable Hardware Research Group (RG EHW)

Department of Computer Systems (DCSY)