Dependable Digital Systems Research Group
Publications
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2024
LOJDA, J.; STRNADEL, J.; ŠIMEK, V.; SMRŽ, P.; HAYES, M.; POPP, R. The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things. Paris: Institute of Electrical and Electronics Engineers, 2024.
p. 0-0. DetailSTRNADEL, J.; LOJDA, J.; SMRŽ, P.; ŠIMEK, V. On SMC-Based Dependability Analysis in LoLiPoP-IoT Project. Limenas Hersonissou: 2024.
p. 0-0. Detail -
2023
LOJDA, J.; PÁNEK, R.; SEKANINA, L.; KOTÁSEK, Z. Automated Design and Usage of the Fault-Tolerant Dynamic Partial Reconfiguration Controller for FPGAs. Microelectronics Reliability, 2023, vol. 2023, no. 144,
p. 1-16. ISSN: 0026-2714. DetailPÁNEK, R.; LOJDA, J. The Fault-tolerant Single-FPGA Systems with a Self-repair Reconfiguration Controller. In LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings. Quito: Institute of Electrical and Electronics Engineers, 2023.
p. 104-107. ISBN: 978-1-6654-5705-7. Detail -
2022
STRNADEL, J. Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking. In Proceedings of 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Prague: Institute of Electrical and Electronics Engineers, 2022.
p. 88-93. ISBN: 978-1-6654-9431-1. Detail -
2021
LOJDA, J.; PÁNEK, R.; KOTÁSEK, Z. Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs. In Proceedings - 2021 24th Euromicro Conference on Digital System Design, DSD 2021. Palermo: Institute of Electrical and Electronics Engineers, 2021.
p. 549-552. ISBN: 978-1-6654-2703-6. DetailLOJDA, J.; PÁNEK, R.; KOTÁSEK, Z. Automatically-Designed Fault-Tolerant Systems: Failed Partitions Recovery. In 2021 IEEE East-West Design and Test Symposium, EWDTS 2021 - Proceedings. Batumi: Institute of Electrical and Electronics Engineers, 2021.
p. 26-33. ISBN: 978-1-6654-4503-0. DetailLOJDA, J.; PÁNEK, R.; PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; KOTÁSEK, Z. Testing Embedded Software Through Fault Injection: Case Study on Smart Lock. In 2021 IEEE 22nd Latin American Test Symposium, LATS 2021. Punta del Este: Institute of Electrical and Electronics Engineers, 2021.
p. 80-85. ISBN: 978-1-6654-2057-0. DetailLOJDA, J.; PODIVÍNSKÝ, J.; ČEKAN, O.; KOTÁSEK, Z. Accelerating Tests of Arithmetic Circuits Through On-FPGA Stimuli Generation and Their Reduction. In International Conference on Electrical, Computer, Communications and Mechatronics Engineering, ICECCME 2021. Mauritius: Institute of Electrical and Electronics Engineers, 2021.
p. 1628-1633. ISBN: 978-1-6654-1262-9. DetailPÁNEK, R.; LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Reliability Analysis of the FPGA Control System with Reconfiguration Hardening. In Proceedings - 2021 24th Euromicro Conference on Digital System Design, DSD 2021. Palermo: Institute of Electrical and Electronics Engineers, 2021.
p. 553-556. ISBN: 978-1-6654-2703-6. DetailSTRNADEL, J. Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults. In Proceedings of 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Vienna: Institute of Electrical and Electronics Engineers, 2021.
p. 111-114. ISBN: 978-1-6654-3595-6. Detail -
2020
LOJDA, J.; PÁNEK, R.; PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; KOTÁSEK, Z. Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock. In 2020 IEEE East-West Design and Test Symposium, EWDTS 2020 - Proceedings. Varna: Institute of Electrical and Electronics Engineers, 2020.
p. 24-28. ISBN: 978-1-7281-9899-6. DetailLOJDA, J.; PÁNEK, R.; PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; KOTÁSEK, Z. Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. In Proceedings - Euromicro Conference on Digital System Design, DSD 2020. Kranj: Institute of Electrical and Electronics Engineers, 2020.
p. 680-683. ISBN: 978-1-7281-9535-3. DetailLOJDA, J.; PODIVÍNSKÝ, J.; ČEKAN, O.; PÁNEK, R.; KRČMA, M.; KOTÁSEK, Z. Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. In Proceedings - 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020. Novi Sad: Institute of Electrical and Electronics Engineers, 2020.
p. 1-4. ISBN: 978-1-7281-9938-2. DetailPÁNEK, R.; LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study. In 2020 International Symposium on VLSI Design, Automation, and Test (VLSI-DAT) : proceedings of technical papers. Hsinchu: IEEE Computer Society, 2020.
p. 121-124. ISBN: 978-1-7281-6083-2. DetailPODIVÍNSKÝ, J.; LOJDA, J.; PÁNEK, R.; ČEKAN, O.; KRČMA, M.; KOTÁSEK, Z. Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks. In 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS). San José: IEEE Circuits and Systems Society, 2020.
p. 1-4. ISBN: 978-1-7281-3427-7. DetailSTRNADEL, J. Statistical Model Checking of Approximate Circuits: Challenges and Opportunities. In Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). Grenoble: IEEE Computer Society, 2020.
p. 1574-1577. ISBN: 978-3-9819263-4-7. Detail -
2019
ČEKAN, O.; PODIVÍNSKÝ, J.; LOJDA, J.; PÁNEK, R.; KRČMA, M.; KOTÁSEK, Z. Smart Electronic Locks and Their Reliability. Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy: Czech Technical University, 2019.
p. 4-5. ISBN: 978-80-01-06607-2. DetailČEKAN, O.; PODIVÍNSKÝ, J.; LOJDA, J.; PÁNEK, R.; KRČMA, M.; KOTÁSEK, Z. Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. In Proceedings of the 2019 22nd Euromicro Conference on Digital System Design. Kalithea: Institute of Electrical and Electronics Engineers, 2019.
p. 506-513. ISBN: 978-1-7281-2861-0. DetailKRČMA, M.; KOTÁSEK, Z.; LOJDA, J. Detecting hard synapses faults in artificial neural networks. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago de Chile: IEEE Computer Society, 2019.
p. 1-6. ISBN: 978-1-7281-1756-0. DetailLOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019.
p. 93-96. ISBN: 978-1-7281-1756-0. DetailPODIVÍNSKÝ, J.; LOJDA, J.; KOTÁSEK, Z. Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019.
p. 97-100. ISBN: 978-1-7281-1756-0. DetailSTRNADEL, J. Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates. In Design, Automation & Test in Europe Conference & Exhibition (DATE). Florence: IEEE Computer Society, 2019.
p. 614-617. ISBN: 978-3-9819263-2-3. DetailSZURMAN, K.; KOTÁSEK, Z. Fault Recovery for Coarse-Grained TMR Soft-Core Processor Using Partial Reconfiguration and State Synchronization. Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2019.
p. 6-7. ISBN: 978-80-01-06607-2. DetailSZURMAN, K.; KOTÁSEK, Z. Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019.
p. 32-35. ISBN: 978-1-7281-1756-0. DetailSZURMAN, K.; KOTÁSEK, Z. Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor neo430. In 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019). Cluj-Napoca: IEEE Computer Society, 2019.
p. 136-140. ISBN: 978-1-7281-0073-9. Detail -
2018
ČEKAN, O.; KOTÁSEK, Z. Random Test Generation Through a Probabilistic Constrained Grammar. INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Budapešť: 2018.
p. 5-8. DetailČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z. Input and Output Generation for the Verification of ALU: a Use Case. In Proceedings of 2018 IEEE East-West Design and Test Symposium, EWDTS 2018. Kazan: IEEE Computer Society, 2018.
p. 331-336. ISBN: 978-1-5386-5710-2. DetailČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Program Generation Through a Probabilistic Constrained Grammar. In Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018. Praha: IEEE Computer Society, 2018.
p. 214-220. ISBN: 978-1-5386-7376-8. DetailLOJDA, J.; KOTÁSEK, Z. Automatizace návrhu spolehlivých systémů a její dílčí komponenty. Počítačové architektury & diagnostika 2018. Stachy: Západočeská univerzita v Plzni, 2018.
s. 5-8. ISBN: 978-80-261-0814-6. DetailLOJDA, J.; KOTÁSEK, Z. Fault Tolerance in HLS for the Purposes of Reliable System Design Automation. Proceedings of the 6th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2018.
p. 31-32. ISBN: 978-80-01-06456-6. DetailLOJDA, J.; PODIVÍNSKÝ, J.; ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z. FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant Systems Design Automation. In Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018.
p. 244-251. ISBN: 978-1-5386-7376-8. DetailLOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. In Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018.
p. 80-86. ISBN: 978-1-5386-5710-2. DetailLOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z.; KRČMA, M. Majority Type and Redundancy Level Influences on Redundant Data Types Approach for HLS. In 2018 16th Biennial Baltic Electronics Conference (BEC). Tallinn: IEEE Computer Society, 2018.
p. 1-4. ISBN: 978-1-5386-7312-6. DetailPÁNEK, R. Metodika návrhu řadiče rekonfigurace pro Systémy odolné proti poruchám. Počítačové architektury & diagnostika 2018. Stachy: Západočeská univerzita v Plzni, 2018.
s. 21-24. ISBN: 978-80-261-0814-6. DetailPÁNEK, R.; LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. In Proceedings of IEEE East-West Design & Test Symposium. Kazaň: IEEE Computer Society, 2018.
p. 129-134. ISBN: 978-1-5386-5710-2. DetailPODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; BURGET, R.; HRUŠKA, T.; KOTÁSEK, Z. A Framework for Optimizing a Processor to Selected Application. In Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018.
p. 564-574. ISBN: 978-1-5386-5710-2. DetailPODIVÍNSKÝ, J.; KOTÁSEK, Z. Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. Proceedings of the 6th Prague Embedded Systems Workshop. Roztoky u Prahy: Czech Technical University, 2018.
p. 33-34. ISBN: 978-80-01-06456-6. DetailPODIVÍNSKÝ, J.; LOJDA, J.; ČEKAN, O.; KOTÁSEK, Z. Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. In Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018.
p. 229-236. ISBN: 978-1-5386-7376-8. DetailPODIVÍNSKÝ, J.; LOJDA, J.; KOTÁSEK, Z. FPGA-based Robot Controller: An Experimental Evaluation of Fault Tolerance Properties. INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Budapešť: 2018.
p. 9-12. DetailPODIVÍNSKÝ, J.; LOJDA, J.; KOTÁSEK, Z. An Experimental Evaluation of Fault-Tolerant FPGA-based Robot Controller. In Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018.
p. 63-69. ISBN: 978-1-5386-5710-2. DetailSTRNADEL, J. Predictability Analysis of Interruptible Systems by Statistical Model Checking. IEEE Design and Test, 2018, vol. 35, no. 2,
p. 57-63. ISSN: 2168-2356. DetailSTRNADEL, J. Statistical Model Checking of Processor Systems in Various Interrupt Scenarios. In Proceedings of 8th International Symposium On Leveraging Applications of Formal Methods, Verification and Validation (ISoLA). Lecture Notes in Computer Science. Lecture Notes in Computer Science, Vol. 11245. Cham: Springer International Publishing, 2018.
p. 414-429. ISSN: 0302-9743. Detail -
2017
ČEKAN, O.; KOTÁSEK, Z. Random Test Stimuli Generation Based on a Probabilistic Grammar. Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017.
p. 43-44. ISBN: 978-80-01-06178-7. DetailČEKAN, O.; KOTÁSEK, Z. A Probabilistic Context-Free Grammar Based Random Test Program Generation. In Proceedings of 20th Euromicro Conference on Digital System Design. Vídeň: Technical University Wien, 2017.
p. 356-359. ISBN: 978-1-5386-2145-5. DetailKRČMA, M.; KOTÁSEK, Z. Approximation accuracy of different FPNN types. Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017.
p. 81-82. ISBN: 978-80-01-06178-7. DetailKRČMA, M.; KOTÁSEK, Z.; LOJDA, J. Comparison of FPNNs Models Approximation Capabilities and FPGA Resources Utilization. In Proceedings of IEEE 13th International Conference on Intelligent Computer Communication and Processing. Cluj-Nappoca: IEEE Computer Society, 2017.
p. 125-132. ISBN: 978-1-5386-3368-7. DetailKRČMA, M.; LOJDA, J.; KOTÁSEK, Z. Triple Modular Redundancy Used in Field Programmable Neural Networks. In Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017.
p. 1-6. ISBN: 978-1-5386-3299-4. DetailLOJDA, J.; KOTÁSEK, Z. A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation. Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017.
p. 79-80. ISBN: 978-80-01-06178-7. DetailLOJDA, J.; KOTÁSEK, Z. Automatizace návrhu systémů odolných proti poruchám pomocí vysokoúrovňové syntézy. Počítačové architektury & diagnostika 2017. Smolenice: Slovenská technická univerzita v Bratislavě, 2017.
s. 59-62. ISBN: 978-80-972784-0-3. DetailLOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Redundant Data Types and Operations in HLS and their Use for a Robot Controller Unit Fault Tolerance Evaluation. In Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017.
p. 359-364. ISBN: 978-1-5386-3299-4. DetailLOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z.; KRČMA, M. Data Types and Operations Modifications: a Practical Approach to Fault Tolerance in HLS. In Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017.
p. 273-278. ISBN: 978-1-5386-3299-4. DetailPÁNEK, R. Systémy odolné proti poruchám - metodika návrhu řadiče rekonfigurace. Počítačové architektury & diagnostika 2017. Smolenice: Slovenská technická univerzita v Bratislavě, 2017.
s. 24-27. ISBN: 978-80-972784-0-3. DetailPODIVÍNSKÝ, J.; ČEKAN, O.; LOJDA, J.; ZACHARIÁŠOVÁ, M.; KRČMA, M.; KOTÁSEK, Z. Functional Verification Based Platform for Evaluating Fault Tolerance Properties. Microprocessors and Microsystems, 2017, vol. 52, no. 5,
p. 145-159. ISSN: 0141-9331. DetailPODIVÍNSKÝ, J.; KOTÁSEK, Z. The Use of Functional Verification for Monitoring Impact of Faults in SRAM-based FPGAs. Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017.
p. 81-82. ISBN: 978-80-01-06178-7. DetailPODIVÍNSKÝ, J.; LOJDA, J.; ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z. Reliability Analysis and Improvement of FPGA-based Robot Controller. In Proceedings of the 2017 20th Euromicro Conference on Digital System Design. Vídeň: IEEE Computer Society, 2017.
p. 337-344. ISBN: 978-1-5386-2145-5. DetailSTRNADEL, J. On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking. In Proceedings of the 2017 20th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2017.
p. 352-355. ISBN: 978-1-5386-2146-2. DetailSZURMAN, K.; KOTÁSEK, Z. State Synchronization of Faulty Soft Core Processors in Reconfigurable TMR Architecture. Počítačové architektúry & diagnostika 2017. Smolenice: Slovak University of Technology in Bratislava, 2017.
p. 51-54. ISBN: 978-80-972784-0-3. Detail -
2016
ČEKAN, O. Generování testovacích stimulů. Počítačové architektury a diagnostika PAD 2016. Bořetice - Kraví Hora: Fakulta informačních technologií VUT v Brně, 2016.
s. 97-100. ISBN: 978-80-214-5376-0. DetailČEKAN, O.; KOTÁSEK, Z. Software-implemented Fault-Tolerant Program Generation. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy: 2016.
p. 13-13. ISBN: 978-80-01-05984-5. DetailČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Random Stimuli Generation Based on a Stochastic Context-Free Grammar. In Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016.
p. 295-296. ISBN: 978-1-5090-5602-6. DetailKOTÁSEK, Z.; PODIVÍNSKÝ, J. Verification of Robot Controller for Evaluating Impacts of Faults in Electro-mechanical Systems. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy: 2016.
p. 0-0. DetailKRČMA, M.; KOTÁSEK, Z.; LOJDA, J.; KAŠTIL, J. Comparsion of FPNNs models approximation capabilities and resources utilization. Proceedings of the Work in progress Session held in connection with DSD 2016. Limassol: Johannes Kepler University Linz, 2016.
p. 1-2. ISBN: 978-3-902457-46-2. DetailLOJDA, J.; KOTÁSEK, Z. A Systematic Approach to the Description of Fault-tolerant Systems. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy: 2016.
p. 0-0. DetailLOJDA, J.; PODIVÍNSKÝ, J.; KRČMA, M.; KOTÁSEK, Z. HLS-based Fault Tolerance Approach for SRAM-based FPGAs. In Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016.
p. 301-302. ISBN: 978-1-5090-5602-6. DetailPODIVÍNSKÝ, J. Funkční verifikace jako nástroj pro sledování vlivu poruch na elektro-mechanický systém. Počítačové architektury a diagnostika PAD 2016. Bořetice - Kraví Hora: Fakulta informačních technologií VUT v Brně, 2016.
s. 101-104. ISBN: 978-80-214-5376-0. DetailPODIVÍNSKÝ, J.; ČEKAN, O.; LOJDA, J.; KOTÁSEK, Z. Functional Verification as a Tool for Monitoring Impact of Faults in SRAM-based FPGAs. In Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016.
p. 293-294. ISBN: 978-1-5090-5602-6. DetailPODIVÍNSKÝ, J.; ČEKAN, O.; LOJDA, J.; KOTÁSEK, Z. Verification of Robot Controller for Evaluating Impacts of Faults in Electro-mechanical Systems. In Proceedings of the 19th Euromicro Conference on Digital Systems Design. Limassol: IEEE Computer Society, 2016.
p. 487-494. ISBN: 978-1-5090-2816-0. DetailRIŠA, M. Scheduling and Synchronization on Multicores. Sborník příspěvků Česko-slovenského semináře pro studenty doktorského studia Počítačové architektury & diagnostika. Brno: Faculty of Information Technology BUT, 2016.
p. 10-13. ISBN: 978-80-214-5376-0. DetailSTRNADEL, J. Modeling and Analysis of Fault-Tolerant Systems by Means of UPPAAL SMC: Method and Benefits. Informal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Bratislava: Slovak University of Technology in Bratislava, 2016.
p. 32-37. ISBN: 978-80-8086-256-5. DetailSTRNADEL, J. On Creation and Analysis of Reliability Models by Means of Stochastic Timed Automata and Statistical Model Checking: Principle. In Leveraging Applications of Formal Methods, Verification and Validation: Foundational Techniques. Lecture Notes in Computer Science. Lecture Notes in Computer Science, Vol. 9952. Cham: Springer International Publishing, 2016.
p. 166-181. ISBN: 978-3-319-47166-2. ISSN: 0302-9743. DetailSTRNADEL, J.; RIŠA, M. On Analysis of Software Interrupt Limiters for Embedded Systems by Means of UPPAAL SMC. In Proceedings of the 24th Austrian Workshop on Microelectronics. Villach: IEEE Computer Society Press, 2016.
p. 45-50. ISBN: 978-1-5090-1040-0. DetailZACHARIÁŠOVÁ, M.; KEKELYOVÁ, M.; KOTÁSEK, Z. Regression Test Suites Optimization for Application-specific Instruction-set Processors and Their Use for Dependability Analysis. In Proceedings of the 19th Euromicro Conference on Digital Systems Design. Limassol Cyprus: IEEE Computer Society, 2016.
p. 380-387. ISBN: 978-1-5090-2816-0. Detail -
2015
ČEKAN, O. Principy generování verifikačních stimulů. Počítačové architektury a diagnostika PAD 2015. Zlín: Fakulta aplikované informatiky, Univerzita Tomáše Bati ve Zlíně, 2015.
s. 13-18. ISBN: 978-80-7454-522-1. DetailČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Software Fault Tolerance: the Evaluation by Functional Verification. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015.
p. 284-287. ISBN: 978-1-4673-8035-5. DetailČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Universal Pseudo-random Generation of Assembler Codes for Processors. Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015.
p. 70-73. DetailKRČMA, M. FPNN - neuronové sítě v FPGA. Počítačové architektury a diagnostika PAD 2015. Zlín: Univerzita Tomáše Bati ve Zlíně, 2015.
s. 81-86. ISBN: 978-80-7454-522-1. DetailKRČMA, M.; KAŠTIL, J.; KOTÁSEK, Z. Mapping trained neural networks to FPNNs. In IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015.
p. 157-160. ISBN: 978-1-4799-6779-7. DetailKRČMA, M.; KOTÁSEK, Z.; KAŠTIL, J. Fault Tolerant Field Programmable Neural Networks. In 1st IEEE Nordic Circuits and Systems (NORCAS) Conference. Oslo: IEEE Computer Society, 2015.
p. 1-4. ISBN: 978-1-4673-6575-8. DetailPODIVÍNSKÝ, J. Využití funkční verifikace pro ověřování metodik pro zajištění odolnosti proti poruchám. Počítačové architektury a diagnostika PAD 2015. Zlín: Univerzita Tomáše Bati ve Zlíně, 2015.
s. 7-12. ISBN: 978-80-7454-522-1. DetailPODIVÍNSKÝ, J.; ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. Microprocessors and Microsystems, 2015, vol. 39, no. 8,
p. 1215-1230. ISSN: 0141-9331. DetailPODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; ČEKAN, O.; KOTÁSEK, Z. FPGA Prototyping and Accelerated Verification of ASIPs. In IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015.
p. 145-148. ISBN: 978-1-4799-6780-3. DetailPODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Radiation Impact on Mechanical Application Driven by FPGA-based Controller. Proceedings of The Fourth Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015.
p. 13-16. DetailSTRNADEL, J. Comparison of Generally Applicable Mechanisms for Preventing Embedded Event-Driven Real-Time Systems from Interrupt Overloads. In Proceedings of the 2015 4th Eastern European Regional Conference on the Engineering of Computer Based Systems. Brno: Brno University of Technology, 2015.
p. 39-44. ISBN: 978-1-4673-7967-0. DetailZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Automation and Optimization of Coverage-driven Verification. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015.
p. 87-94. ISBN: 978-1-4673-8035-5. Detail -
2014
ČEKAN, O. Universal Generation of Test Vectors for Functional Verification. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014.
p. 44-49. ISBN: 978-80-7494-027-9. DetailČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Solving of Constraint Satisfaction Problem. Proceedings of the 20th Conference STUDENT EEICT 2014. Volume 3. Brno: Faculty of Information Technology BUT, 2014.
p. 291-295. ISBN: 978-80-214-4924-4. DetailKOTÁSEK, Z.; MIČULKA, L. Generic Partial Dynamic Reconfiguration Controller for Transient and Permanent Fault Mitigation in Fault Tolerant Systems Implemented Into FPGA. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014.
p. 171-174. ISBN: 978-0-7695-5074-9. DetailMATUŠOVÁ, L.; KAŠTIL, J.; KOTÁSEK, Z. Automatic Construction of On-line Checking Circuits Based on Finite Automata. In 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014.
p. 326-332. ISBN: 978-0-7695-5074-9. DetailPODIVÍNSKÝ, J. Testing Fault-Tolerance Properties in FPGA based Electro-mechanical Applications. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014.
p. 13-18. ISBN: 978-80-7494-027-9. DetailPODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Complex Control System for Testing Fault-Tolerance Methodologies. Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Dresden: COST, European Cooperation in Science and Technology, 2014.
p. 24-27. ISBN: 978-2-11-129175-1. DetailSTRNADEL, J.; POKORNÝ, M. Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework. In Proceedings of the 2014 17th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2014.
p. 333-340. ISBN: 978-1-4799-5793-4. DetailSTRNADEL, J.; SLIMAŘÍK, F. Impact of Software Fault Tolerance to Fault Effects in OS-Driven RT Systems. Computing and Informatics, 2014, vol. 33, no. 4,
p. 757-782. ISSN: 1335-9150. DetailSZURMAN, K. Synchronization Methodology for Fault Tolerant System Recovery After Its Failure. Počítačové architektury & diagnostika 2014. Malá Skála: Liberec University of Technology, 2014.
p. 111-116. ISBN: 978-80-7494-027-9. DetailZACHARIÁŠOVÁ, M. Application of Evolutionary Computing for Optimization of Functional Verification. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014.
p. 135-140. ISBN: 978-80-7494-027-9. Detail -
2013
MIČULKA, L. Metoda návrh systémů odolných proti poruchám do omezeného implementačního prostoru na bázi FPGA. Počítačové architektury & diagnostika 2013. Plzeň: Západočeská univerzita v Plzni, 2013.
s. 63-68. ISBN: 978-80-261-0270-0. DetailMIČULKA, L.; STRAKA, M.; KOTÁSEK, Z. Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area. 16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Santander: IEEE Computer Society, 2013.
p. 227-234. ISBN: 978-0-7695-5074-9. DetailSTRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z.; MIČULKA, L. Fault Tolerant System Design and SEU Injection based Testing. Microprocessors and Microsystems, 2013, vol. 2013, no. 37,
p. 155-173. ISSN: 0141-9331. DetailSTRNADEL, J. Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates. Architecture of Computing Systems - ARCS 2013. Lecture Notes in Computer Science. Lecture Notes in Computer Science, ISSN 0302-9743, Vol. 7767. Berlin: Springer Verlag, 2013.
p. 98-109. ISBN: 978-3-642-36423-5. ISSN: 0302-9743. DetailSTRNADEL, J. On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems. Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Brno: IEEE Computer Society, 2013.
p. 24-29. ISBN: 978-1-4673-6133-0. DetailSZURMAN, K. Fault Tolerant CAN Bus Control System Implemented into FPGA and its synchronization after failure and recovery. Počítačové architektury & diagnostika 2013. Plzeň: University of West Bohemia in Pilsen, 2013.
p. 21-26. ISBN: 978-1-4673-6136-1. DetailZACHARIÁŠOVÁ, M. New Methods for Increasing Efficiency and Speed of Functional Verification. Počítačové architektury a diagnostika PAD 2013. Plzeň: University of West Bohemia in Pilsen, 2013.
p. 111-116. ISBN: 978-80-261-0270-0. DetailZACHARIÁŠOVÁ, M.; BOLCHINI, C.; KOTÁSEK, Z. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Karlovy Vary: IEEE Computer Society, 2013.
p. 275-278. ISBN: 978-1-4673-6133-0. DetailZACHARIÁŠOVÁ, M.; BOLCHINI, C.; KOTÁSEK, Z. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. Proceedings of The Second Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Avignon: COST, European Cooperation in Science and Technology, 2013.
p. 35-38. ISBN: 978-2-11-129175-1. DetailZACHARIÁŠOVÁ, M.; PŘIKRYL, Z.; HRUŠKA, T.; KOTÁSEK, Z. Automated Functional Verification of Application Specific Instruction-set Processors. IFIP Advances in Information and Communication Technology, 2013, vol. 4, no. 403,
p. 128-138. ISSN: 1868-4238. Detail -
2012
KAŠTIL, J.; STRAKA, M.; MIČULKA, L.; KOTÁSEK, Z. Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Cesme-Izmir: IEEE Computer Society, 2012.
p. 250-257. ISBN: 978-0-7695-4798-5. DetailKOTÁSEK, Z.; ŠKARVADA, J. Low Power Testing. In Design and Test Technology foír Dependable Systems-on-Chip. Hershey: IGI Global, 2012.
p. 395-412. ISBN: 978-1-60960-212-3. DetailMIČULKA, L. Metoda návrh systémů odolných proti poruchám do omezeného implementačního prostoru na bázi FPGA. Počítačové architektury & diagnostika 2012. Praha: Fakulta informačních technologií ČVUT, 2012.
s. 109-115. ISBN: 978-80-01-05106-1. DetailMIČULKA, L.; KOTÁSEK, Z. Design Sychronization after Partial Dynamic Reconfiguration of Fault Tolerant System. 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Cesme-Izmir: IEEE Computer Society, 2012.
p. 20-21. ISBN: 978-3-902457-33-2. DetailSTRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Methodology for Reliability Analysis of FPGA-based Fault Tolerant Systems. CSE'2012 International Scientific Conference on Computer Science and Engineering. Košice: The University of Technology Košice, 2012.
p. 146-153. ISBN: 978-80-8143-049-7. DetailSTRAKA, M.; MIČULKA, L.; KAŠTIL, J.; KOTÁSEK, Z. Test Platform for Fault Tolerant Systems Design Qualities Verification. 15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Tallin: IEEE Computer Society, 2012.
p. 336-341. ISBN: 978-1-4673-1185-4. DetailSTRNADEL, J. Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems. In Proceedings of the 15th International IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Tallin: IEEE Computer Society, 2012.
p. 121-126. ISBN: 978-1-4673-1188-5. DetailSTRNADEL, J.; RAJNOHA, P. Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study. Acta Electrotechnica et Informatica, 2012, vol. 12, no. 4,
p. 17-29. ISSN: 1335-8243. DetailSTRNADEL, J.; SLIMAŘÍK, F. On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels. Proceedings of the 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Pistacaway: IEEE Computer Society, 2012.
p. 272-279. ISBN: 978-0-7695-4798-5. DetailZACHARIÁŠOVÁ, M. Acceleration of Functional Verification in the Development Cycle of Hardware Systems. Počítačové architektury a diagnostika. Praha: Czech Technical University, 2012.
p. 73-78. ISBN: 978-80-01-05106-1. Detail -
2011
BARTOŠ, P. Metody reorganizace řetězce scan. Počítačové architektury a diagnostika 2011. Bratislava: Vydavateľstvo STU, 2011.
s. 97-102. ISBN: 978-80-227-3552-0. DetailBARTOŠ, P. Test Time Reduction by Scan Chain Reordering. Proceedings of the 17th Conference STUDENT EEICT 2011. Volume 3. Brno: Faculty of Electrical Engineering and Communication BUT, 2011.
p. 564-568. ISBN: 978-80-214-4273-3. DetailBARTOŠ, P.; KOTÁSEK, Z.; DOHNAL, J. Decreasing Test Time by Scan Chain Reorganization. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011.
p. 371-374. ISBN: 978-1-4244-9753-9. DetailRUMPLÍK, M.; STRNADEL, J. On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits. Proceedings of the 14th Euromicro Conference on Digital System Design - Architectures, Methods and Tools 2011. Oulu: IEEE Computer Society, 2011.
p. 367-374. ISBN: 978-0-7695-4494-6. DetailSTRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems. 14th EUROMICRO Conference on Digital System Design. Oulu: IEEE Computer Society, 2011.
p. 223-230. ISBN: 978-0-7695-4494-6. DetailSTRAKA, M.; KAŠTIL, J.; NOVOTNÝ, J.; KOTÁSEK, Z. Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011.
p. 397-398. ISBN: 978-1-4244-9753-9. DetailSTRNADEL, J. Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads. Proceedings of the Work in Progress Session held in connection with SEAA 2011, the 37th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2011, the 14th EUROMICRO Conference on Digital System Design. Oulu: Johannes Kepler University Linz, 2011.
p. 21-22. ISBN: 978-3-902457-30-1. DetailSTRNADEL, J. Návrh časově kritických systémů III: priorita úloh. Automa, 2011, roč. 2011, č. 2,
s. 50-52. ISSN: 1210-9592. DetailSTRNADEL, J. Návrh časově kritických systémů IV: realizace prostředky RTOS. Automa, 2011, roč. 2011, č. 4,
s. 58-60. ISSN: 1210-9592. Detail -
2010
KOTÁSEK, Z.; ŠKARVADA, J.; STRNADEL, J. Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences. Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010.
p. 364-369. ISBN: 978-1-4244-6610-8. DetailKOTÁSEK, Z.; ŠKARVADA, J.; STRNADEL, J. The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. Proceedings of 13th Euromicro Conference on Digital System Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2010.
p. 644-651. ISBN: 978-0-7695-4171-6. DetailŠKARVADA, J.; KOTÁSEK, Z.; STRNADEL, J. Optimalizace aplikace testu číslicových systémů pro nízký příkon. Brno: Fakulta informačních technologií VUT v Brně, 2010. 142 s. ISBN: 978-80-214-4209-2. Detail
ŠKARVADA, J.; KOTÁSEK, Z.; STRNADEL, J. The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Lecture Notes in Computer Science, ISSN 0302-9743, Vol. 6274. Berlin: Springer Verlag, 2010.
p. 181-192. ISBN: 978-3-642-15322-8. ISSN: 0302-9743. DetailSTRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration. 13th EUROMICRO Conference on Digital System Design, DSD'2010. Lille: IEEE Computer Society, 2010.
p. 365-372. ISBN: 978-0-7695-4171-6. DetailSTRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA. NORCHIP 2010. Tampere: IEEE Computer Society, 2010.
p. 1-4. ISBN: 978-1-4244-8971-8. DetailSTRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Methodology for Design of Highly Dependable Systems in FPGA. International Scientific Conference on Computer Science and Engineering. Košice: The University of Technology Košice, 2010.
p. 186-193. ISBN: 978-80-8086-164-3. DetailSTRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs. Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Wien: IEEE Computer Society, 2010.
p. 173-176. ISBN: 978-1-4244-6610-8. DetailSTRNADEL, J. Task-Level Modeling and Design of Components for Construction of Dependable Time-Critical Systems Implemented by Means of RT Kernel. Sborník přednášek z 33. mezinárodní konference TD 2010 - DIAGON 2010. Zlín: Tomas Bata University in Zlín, 2010.
p. 99-104. ISBN: 978-80-7318-940-2. DetailSTRNADEL, J. Návrh časově kritických systémů I: specifikace a verifikace. Automa, 2010, roč. 2010, č. 10,
s. 42-44. ISSN: 1210-9592. DetailSTRNADEL, J. Návrh časově kritických systémů II: úlohy reálného času. Automa, 2010, roč. 2010, č. 12,
s. 18-19. ISSN: 1210-9592. Detail -
2009
KOTÁSEK, Z.; STRAKA, M. The Design of On-line Checkers and Their Use in Verification and Testing. Acta Electrotechnica et Informatica, 2009, vol. 2009, no. 3,
p. 8-15. ISSN: 1335-8243. DetailSTRAKA, M.; KOTÁSEK, Z. High Availability Fault Tolerant Architectures Implemented into FPGAs. 12th EUROMICRO Conference on Digital System Design DSD 2009. Patras: IEEE Computer Society, 2009.
p. 108-116. ISBN: 978-0-7695-3782-5. DetailSTRAKA, M.; KOTÁSEK, Z. Reliability Models for Fault Tolerant Architectures Based on FPGA. 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Faculty of Informatics MU, 2009.
p. 239-239. ISBN: 978-80-87342-04-6. DetailSTRNADEL, J. Overview of Mechanisms for Improving Reliability of Embedded Real-Time Systems. Proceedings of 32th International Conference TD - DIAGON 2009. Zlín: Tomas Bata University in Zlín, 2009.
p. 19-24. ISBN: 978-80-7318-840-5. DetailSTRNADEL, J.; RŮŽIČKA, R. Testability Analysis Driven Data Path Modification And Controller Synthesis. Proceedings of 16th Electronic Devices and Systems IMAPS CS International Conference. Brno: Brno University of Technology, 2009.
p. 363-368. ISBN: 978-80-214-3933-7. Detail -
2008
HERRMAN, T. Identifikace testovatelných bloků v obvodu na úrovni RT. Počítačové architektury a diagnostika 2008. Liberec: Technická univerzita v Liberci, 2008.
s. 25-35. ISBN: 978-80-7372-378-1. DetailPEČENKA, T. Prostředky a metody pro automatické generování testovacích obvodů. Brno: Fakulta informačních technologií VUT v Brně, 2008. 141 s. ISBN: 978-80-214-3603-9. Detail
PEČENKA, T.; SEKANINA, L.; KOTÁSEK, Z. Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2008, vol. 13, no. 3,
p. 1-21. ISSN: 1084-4309. DetailSEKANINA, L.; STAREČEK, L.; KOTÁSEK, Z.; GAJDA, Z. Polymorphic Gates in Design and Test of Digital Circuits. International Journal of Unconventional Computing, 2008, vol. 4, no. 2,
p. 125-142. ISSN: 1548-7199. DetailŠKARVADA, J. Optimalizace testu pro nízký příkon. Počítačové architektury a diagnostika 2008. Liberec: Technická univerzita v Liberci, 2008.
s. 103-111. ISBN: 978-80-7372-378-1. DetailŠKARVADA, J.; KOTÁSEK, Z.; HERRMAN, T. Power Conscious RTL Test Scheduling. 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2008.
p. 265-265. ISBN: 978-80-7355-082-0. DetailŠKARVADA, J.; KOTÁSEK, Z.; HERRMAN, T. Power Conscious RTL Test Scheduling. Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2008.
p. 721-728. ISBN: 978-0-7695-3277-6. DetailŠKARVADA, J.; KOTÁSEK, Z.; HERRMAN, T. Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. Microprocessors and Microsystems, 2008, vol. 32, no. 5,
p. 296-302. ISSN: 0141-9331. DetailSTAREČEK, L.; SEKANINA, L.; KOTÁSEK, Z. Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008.
p. 255-258. ISBN: 978-1-4244-2276-0. DetailSTRAKA, M. Checkers Design for Communication Protocols Based on FPGAs. Proceedings of the 14th Conference STUDENT EEICT 2008 Volume 4. Brno: Faculty of Information Technology BUT, 2008.
p. 467-473. ISBN: 978-80-214-3617-6. DetailSTRAKA, M.; KOTÁSEK, Z. Design of FPGA-Based Dependable Systems. 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2008.
p. 240-247. ISBN: 978-80-7355-082-0. DetailSTRAKA, M.; KOTÁSEK, Z.; WINTER, J. Digital Systems Architectures Based on On-line Checkers. 11th EUROMICRO Conference on Digital System Design DSD 2008. Parma: IEEE Computer Society, 2008.
p. 81-87. ISBN: 978-0-7695-3277-6. DetailSTRNADEL, J. Analýza a zlepšení testovatelnosti číslicových obvodů na úrovni meziregistrových přenosů. Brno: Fakulta informačních technologií VUT v Brně, 2008. 187 s. ISBN: 978-80-214-3599-5. Detail
STRNADEL, J. TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path. Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2008.
p. 865-872. ISBN: 978-0-7695-3277-6. DetailSTRNADEL, J. Testability Enhancement of Multilevel Designs Guided by Testability Analysis Method. Proceedings of Electronic Devices and Systems IMAPS CS International Conference. Brno: Brno University of Technology, 2008.
p. 367-372. ISBN: 978-80-214-3717-3. DetailSTRNADEL, J.; PEČENKA, T.; KOTÁSEK, Z. Measuring Design for Testability Tool Effectiveness by Means of FITTest_BENCH06 Benchmark Circuits. Computing and Informatics, 2008, vol. 27, no. 6,
p. 913-930. ISSN: 1335-9150. Detail -
2007
HERRMAN, T. Metodika identifikace Testovatelných bloků v obvodu na úrovni RT. Počítačové architektury a diagnostika 2007. Plzeň: Západočeská univerzita v Plzni, 2007.
s. 67-76. ISBN: 978-80-7043-605-9. DetailHERRMAN, T. Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. MEMICS proceedings 2007. Brno: Ing. Zdeněk Novotný, CSc., 2007.
p. 269-269. ISBN: 978-80-7355-077-6. DetailKOTÁSEK, Z.; KUBEK, J. Finite State Machine Localisation Based on IP Softcores Analysis. 6th Electronic Circuits and Systems Conference. Conference Proceedings. Bratislava: Slovak University of Technology in Bratislava, 2007.
p. 137-142. ISBN: 978-80-227-2697-9. DetailRŮŽIČKA, R. Podpora návrhu pro snadnou testovatelnost číslicových obvodů popsaných na úrovni meziregistrových přenosů. Brno: Fakulta informačních technologií VUT v Brně, 2007. 130 s. ISBN: 978-80-214-3551-3. Detail
RŮŽIČKA, R.; STRNADEL, J. Test Controller Synthesis Constrained by Circuit Testability Analysis. Proceedings of 10th Euromicro Conference on Digital System Design, Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society Press, 2007.
p. 626-633. ISBN: 0-7695-2978-X. DetailŠKARVADA, J. Optimalizace plánování testu vzhledem k příkonu. Počítačové architektury a diagnostika 2007. Plzeň: Západočeská univerzita v Plzni, 2007.
s. 85-92. ISBN: 978-80-7043-605-9. DetailŠKARVADA, J. RT Level Power Consumption Estimation Tool. Proceedings of the 13th Conference STUDENT EEICT 2007 Volume 4. Brno: Brno University of Technology, 2007.
p. 467-471. ISBN: 80-214-3410-3. DetailŠKARVADA, J. RT Level Test Optimization for Low Power Consumption. MEMICS proceedings 2007. Brno: Ing. Zdeněk Novotný, CSc., 2007.
p. 185-192. ISBN: 978-80-7355-077-6. DetailŠKARVADA, J.; HERRMAN, T.; KOTÁSEK, Z. Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. 10th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN Architectures, Methods and Tools (DSD 2007). Lübeck: IEEE Computer Society, 2007.
p. 611-618. ISBN: 0-7695-2978-X. DetailSTRAKA, M. VHDL Design of Educational, Modern and Open-Architecture CPU. Proceedings of the 13th Conference STUDENT EEICT 2007 Volume 4. Brno: Brno University of Technology, 2007.
p. 457-461. ISBN: 978-80-214-3410-3. DetailSTRAKA, M.; TOBOLA, J.; KOTÁSEK, Z. Checker Design for On-line Testing of Xilinx FPGA Communication. The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Rome: IEEE Computer Society, 2007.
p. 152-160. ISBN: 0-7695-2885-6. DetailSTRNADEL, J. Educational Toolset for Experimenting with Optimizations in the Area of Cost/Quality Trade-Offs Related to Digital Circuit Diagnosis. Proceedings of 14th Electronic Devices and Systems IMAPS CS International Conference. Brno: Brno University of Technology, 2007.
p. 333-338. ISBN: 978-80-214-3470-7. DetailSTRNADEL, J. On Encoding and Utilization of Diagnostic Information Extracted from Design-Data for Testability Analysis Purposes. Proceedings of the 6th Electronic Circuits and Systems Conference. Bratislava: Slovak University of Technology in Bratislava, 2007.
p. 171-176. ISBN: 978-80-227-2697-9. DetailTOBOLA, J.; KOTÁSEK, Z.; KOŘENEK, J.; MARTÍNEK, T.; STRAKA, M. Online Protocol Testing for FPGA Based Fault Tolerant Systems. 10th EUROMICRO Conference on Digital System Design DSD 2007. Lubeck, Germany: IEEE Computer Society, 2007.
p. 676-679. ISBN: 0-7695-2978-X. Detail -
2006
HERRMAN, T. Formal Model of Testable Block. Proceedings of 12th Conference Student EEICT 2006, Volume 4. Brno: Faculty of Electrical Engineering and Communication BUT, 2006.
p. 451-455. ISBN: 80-214-3163-6. DetailHERRMAN, T. Metodika aplikace testu obvodu založená na identifikaci Testovatelných bloků. Počítačové architektúry a diagnostika - zborník príspovkov. Bratislava: Ústav informatiky Slovenskej akadémie vied, 2006.
s. 131-136. ISBN: 80-969202-2-7. DetailHERRMAN, T. Testability Analysis Based on Formal Model. Proceedings of the Sevnth International Scientific Conference ECI 2006. Košice: Faculty of Electrical Engineering and Informatics, University of Technology Košice, 2006.
p. 243-248. ISBN: 80-8073-598-0. DetailKOTÁSEK, Z.; STRNADEL, J. SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS). Los Alamitos, CA: IEEE Computer Society, 2006.
p. 497-498. ISBN: 0-7695-2546-6. DetailPEČENKA, T. Prostředky a metody pro automatické vytváření testovacích obvodů. Sborník příspěvků pracovního semináře Počítačové architektury & diagnostika pro studenty doktorského studia. Bratislava: Ústav informatiky Slovenskej akadémie vied, 2006.
s. 13-18. ISBN: 80-969202-2-7. DetailPEČENKA, T.; KOTÁSEK, Z. I-path Scheduling Algorithm for RT Level Circuits. MEMICS 2006 2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Mikulov: 2006.
p. 174-181. ISBN: 80-214-3287-X. DetailPEČENKA, T.; KOTÁSEK, Z.; SEKANINA, L. FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties. Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006.
p. 285-289. ISBN: 1424401844. DetailPEČENKA, T.; STRNADEL, J.; KOTÁSEK, Z.; SEKANINA, L. Testability Estimation Based on Controllability and Observability Parameters. Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06). IEEE CS. Cavtat: IEEE Computer Society, 2006.
p. 504-514. ISBN: 0-7695-2609-8. DetailŠKARVADA, J. GA Based Test Scheduling Under Power Constraints. Proceedings of 12th Conference Student EEICT 2006, Volume 4. Brno: Faculty of Electrical Engineering and Communication BUT, 2006.
p. 461-465. ISBN: 80-214-3163-6. DetailŠKARVADA, J. Optimalizace plánování testu číslicových systémů vzhledem k příkonu. Sborník příspěvků pracovního semináře Počítačové architektury & diagnostika pro studenty doktorského studia. Bratislava: Ústav informatiky Slovenskej akadémie vied, 2006.
s. 143-148. ISBN: 80-9692-0227. DetailŠKARVADA, J. Test Scheduling for SOC under Power Constraints. Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Prague: Czech Technical University Publishing House, 2006.
p. 91-93. ISBN: 1-4244-0184-4. DetailŠKARVADA, J.; RŮŽIČKA, R. Using Petri Nets for RT Level Digital Systems Test Scheduling. Proceedings of 1st International Workshop on Formal Models (WFM'06). Ostrava: 2006.
p. 79-86. ISBN: 80-86840-20-4. DetailSTRNADEL, J. On Distribution of Testability Values in Scan-Layout State-Space. Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics. Košice: The University of Technology Košice, 2006.
p. 308-313. ISBN: 80-8073-598-0. DetailSTRNADEL, J. Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space. Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Prague: Czech Technical University Publishing House, 2006.
p. 161-162. ISBN: 1-4244-0184-4. DetailSTRNADEL, J. Testability Analysis and Improvements of Register-Transfer Level Digital Circuits. Computing and Informatics, 2006, vol. 25, no. 5,
p. 441-464. ISSN: 1335-9150. DetailSTRNADEL, J.; DHALI, A. Novel Optimizing Approach in the Area of STEP-Based Construction of Sessionless, Power-Constrainted, TAM and Time Optimal Test Schedules. Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS). Los Alamitos, CA: IEEE Computer Society, 2006.
p. 360-367. ISBN: 0-7695-2546-6. Detail -
2005
KOTÁSEK, Z.; STRNADEL, J. Testing Tools for Training and Education. Proceedings of 12th International Conference on Mixed Design of Integrated Circuits and Systems. Krakow: Department of Microelectronics and Computer Science, Technical University of Lodz, 2005.
p. 671-676. ISBN: 83-919289-9-3. DetailKOTÁSEK, Z.; STRNADEL, J.; PEČENKA, T. Methodology of Selecting Scan-Based Testability Improving Technique. Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005.
p. 186-189. ISBN: 963-9364-48-7. DetailPEČENKA, T. At-speed testování spojů na kartě COMBO6. Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005.
p. 221-223. ISBN: 963-9364-48-7. DetailPEČENKA, T. Prostředky a metody pro automatické vytváření testovacích obvodů. Sborník příspěvků ze semináře Počítačové Architektury a Diagnostika. Praha: Fakulta elektrotechniky ČVUT, 2005.
s. 135-140. ISBN: 80-01-03298-1. DetailPEČENKA, T.; KOTÁSEK, Z.; SEKANINA, L.; STRNADEL, J. Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2005.
p. 51-58. ISBN: 0-7695-2399-4. DetailRŮŽIČKA, R. A Complex Approach to Digital RTL Circuit Testability - iFCoRT System. Informal Digest of Papers of the IEEE European Test Symposium 2005. Tallinn: Tallinn University of Technology, 2005.
p. 156-157. DetailRŮŽIČKA, R. On the Petri Net Based Test Scheduling. Proceedings of the Work in Progress Session at Euromicro SEAA/DSD 2005. Linz: Johannes Kepler University Linz, 2005.
p. 18-19. ISBN: 3-902457-09-0. DetailSTRNADEL, J. VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements. Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005.
p. 190-193. ISBN: 963-9364-48-7. DetailSTRNADEL, J.; KOTÁSEK, Z. Educational Tool for the Demonstration of Dft Principles Based on Scan Methodologies. Proceedings of 8th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2005.
p. 420-427. ISBN: 0-7695-2433-8. Detail