Lukáš Sekanina

Publications

• 2024

  ARIF, M.; REHMAN, F.; SEKANINA, L.; MALIK, A. A comprehensive survey of evolutionary algorithms and metaheuristics in brain EEG-based applications. Journal of Neural Engineering, 2024, vol. 21, no. 5, p. 1-25. ISSN: 1741-2552. Detail

  HUSA, J.; SEKANINA, L. Semantic Mutation Operator for Fast and Efficient Design of Bent Boolean Functions. Genetic Programming and Evolvable Machines, 2024, vol. 25, no. 3, p. 1-32. ISSN: 1389-2576. Detail

  KLHŮFEK, J.; ŠAFÁŘ, M.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. Exploiting Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. In 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS). Kielce: Institute of Electrical and Electronics Engineers, 2024. p. 1-6. ISBN: 979-8-3503-5934-3. Detail

  SEKANINA, L. Tutorial: Evolutionary Design Methods in Electronic Design Automation. IEEE 42nd International Conference on Computer Design (ICCD). Milano: IEEE Computer Society, 2024. p. 689-690. ISBN: 979-8-3503-8040-8. Detail

  VAŠÍČEK, Z.; MRÁZEK, V.; SEKANINA, L. Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. In 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE). Valencia: Institute of Electrical and Electronics Engineers, 2024. p. 1-6. ISBN: 979-8-3503-4859-0. Detail

• 2023

  HURTA, M.; MRÁZEK, V.; DRAHOŠOVÁ, M.; SEKANINA, L. Multi-objective Design of Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. Evo* 2023 -- Late-Breaking Abstracts Volume. Brno: 2023. p. 0-0. Detail

  HURTA, M.; MRÁZEK, V.; DRAHOŠOVÁ, M.; SEKANINA, L. ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE). Antwerp: Institute of Electrical and Electronics Engineers, 2023. p. 1-2. ISBN: 978-3-9819263-7-8. Detail

  HURTA, M.; MRÁZEK, V.; DRAHOŠOVÁ, M.; SEKANINA, L. MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. In 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Tallinn: Institute of Electrical and Electronics Engineers, 2023. p. 155-160. ISBN: 979-8-3503-3277-3. Detail

  HURTA, M.; SCHWARZEROVÁ, J.; NAGELE, T.; WECKWERTH, W.; PROVAZNÍK, V.; SEKANINA, L. Utilizing Genetic Programming to Enhance Polygenic Risk Score Calculation. In 2023 IEEE International Conference on Bioinformatics and Biomedicine (BIBM 2023). Istanbul: Institute of Electrical and Electronics Engineers, 2023. p. 3782-3787. ISBN: 979-8-3503-3748-8. Detail

  HURTA, M.; SCHWARZEROVÁ, J.; PROVAZNÍK, V.; WECKWERTH, W.; WALTHER, D.; SEKANINA, L. Utilizing Cartesian Genetic Programming for Efficient Polygenic Risk Score Calculation in Plants. Program and Abstract Book: Swedish Bioinformatics Workshop 2023. Stockholm: 2023. p. 49-49. Detail

  HUSA, J.; SEKANINA, L. Semantic Mutation Operator for Fast and Efficient Design of Bent Boolean Functions. Evo* 2023 -- Late-Breaking Abstracts Volume. Brno: 2023. p. 0-0. Detail

  JŮZA, T.; SEKANINA, L. GPAM: Genetic Programming with Associative Memory. In 26th European Conference on Genetic Programming (EuroGP) Held as Part of EvoStar. Lecture Notes in Computer Science. LNCS. Cham: Springer Nature Switzerland AG, 2023. p. 68-83. ISBN: 978-3-031-29572-0. ISSN: 0302-9743. Detail

  LOJDA, J.; PÁNEK, R.; SEKANINA, L.; KOTÁSEK, Z. Automated Design and Usage of the Fault-Tolerant Dynamic Partial Reconfiguration Controller for FPGAs. Microelectronics Reliability, 2023, vol. 2023, no. 144, p. 1-16. ISSN: 0026-2714. Detail

  PIŇOS, M.; MRÁZEK, V.; SEKANINA, L. Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. In 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Talinn: Institute of Electrical and Electronics Engineers, 2023. p. 45-50. ISBN: 979-8-3503-3277-3. Detail

  PIŇOS, M.; MRÁZEK, V.; VAVERKA, F.; VAŠÍČEK, Z.; SEKANINA, L. Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2023, vol. 13, no. 1, p. 212-224. ISSN: 2156-3357. Detail

  PRABAKARAN, B.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; SHAFIQUE, M. Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. In 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD). San Francisco: Institute of Electrical and Electronics Engineers, 2023. p. 1-9. ISBN: 979-8-3503-1559-2. Detail

  SEDLÁČEK, M.; SEKANINA, L. Evolution of Editing Scripts From Examples. In Proceedings of the Genetic and Evolutionary Computation Conference Companion (GECCO '23). Lisbon: Association for Computing Machinery, 2023. p. 803-806. ISBN: 979-8-4007-0120-7. Detail

  SEKANINA, L.; MRÁZEK, V.; PIŇOS, M. Hardware-Aware Evolutionary Approaches to Deep Neural Networks. In Handbook of Evolutionary Machine Learning. Genetic and Evolutionary Computation. Singapore: Springer Nature Singapore, 2023. p. 367-396. ISBN: 978-981-9938-13-1. Detail

• 2022

  BOSIO, A.; DI CARLO, S.; GIRARD, P.; RUOSPO, A.; SANCHEZ, E.; SAVINO, A.; SEKANINA, L.; TRAIOLA, M.; VAŠÍČEK, Z.; VIRAZEL, A. Design, Verification, Test, and In-Field Implications of Approximate Digital Integrated Circuits. In Approximate Computing Techniques. Cham: Springer International Publishing, 2022. p. 349-385. ISBN: 978-3-030-94704-0. Detail

  ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; SEKANINA, L.; VAŠÍČEK, Z.; VOJNAR, T. SagTree: Towards Efficient Mutation in Evolutionary Circuit Approximation. Swarm and Evolutionary Computation, 2022, vol. 69, no. 100986, p. 1-10. ISSN: 2210-6502. Detail

  HURTA, M.; DRAHOŠOVÁ, M.; SEKANINA, L.; SMITH, S.; ALTY, J. Evolutionary Design of Reduced Precision Levodopa-Induced Dyskinesia Classifiers. In Genetic Programming, 25th European Conference, EuroGP 2022. Lecture Notes in Computer Science. Madrid: Springer Nature Switzerland AG, 2022. p. 85-101. ISBN: 978-3-031-02055-1. Detail

  PIŇOS, M.; MRÁZEK, V.; SEKANINA, L. Evolutionary Approximation and Neural Architecture Search. Genetic Programming and Evolvable Machines, 2022, vol. 23, no. 3, p. 351-374. ISSN: 1389-2576. Detail

  SEKANINA, L.; VAŠÍČEK, Z.; MRÁZEK, V. Inexact Arithmetic Operators. In Approximate Computing Techniques. Cham: Springer International Publishing, 2022. p. 81-107. ISBN: 978-3-030-94704-0. Detail

  VÁLEK, M.; SEKANINA, L. Evolutionary Approximation in Non-Local Means Image Filters. In 2022 IEEE International Conference on Systems, Man, and Cybernetics (SMC). Praha: Institute of Electrical and Electronics Engineers, 2022. p. 2759-2766. ISBN: 978-1-6654-5258-8. Detail

• 2021

  BARBARESCHI, M.; BOSIO, A.; SEKANINA, L.; BRAUN, C. Editorial: Special issue on Advancing on Approximate Computing: Methodologies, Architectures and Algorithms. Future Generation Computer Systems-The International Journal of Grid Computing Theory Methods and Applications. 2021. p. 54-55. ISSN: 0167-739X. Detail

  PIŇOS, M.; MRÁZEK, V.; SEKANINA, L. Evolutionary Neural Architecture Search Supporting Approximate Multipliers. In Genetic Programming, 24th European Conference, EuroGP 2021. Lecture Notes in Computer Science, vol 12691. Seville: Springer Nature Switzerland AG, 2021. p. 82-97. ISBN: 978-3-030-72812-0. Detail

  SEKANINA, L. Evolutionary Algorithms in Approximate Computing: A Survey. Journal of Integrated Circuits and Systems, 2021, vol. 16, no. 2, p. 1-12. ISSN: 1872-0234. Detail

  SEKANINA, L. Neural Architecture Search and Hardware Accelerator Co-Search: A Survey. IEEE Access, 2021, vol. 9, no. 9, p. 151337-151362. ISSN: 2169-3536. Detail

  SHAFIQUE, M.; STEININGER, A.; SEKANINA, L.; KRSTIĆ, M.; STOJANOVIC, G.; MRÁZEK, V. 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. USA: Institute of Electrical and Electronics Engineers, 2021. p. 0-0. ISBN: 978-1-6654-3595-6. Detail

• 2020

  ANSARI, M.; MRÁZEK, V.; COCKBURN, B.; SEKANINA, L.; VAŠÍČEK, Z.; HAN, J. Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Trans. on VLSI Systems., 2020, vol. 28, no. 2, p. 317-328. ISSN: 1063-8210. Detail

  BOSIO, A.; DI CARLO, S.; GIRARD, P.; SANCHEZ, E.; SAVINO, A.; SEKANINA, L.; TRAIOLA, M.; VAŠÍČEK, Z.; VIRAZEL, A. Design, Verification, Test and In-Field Implications of Approximate Computing Systems. In 25th IEEE European Test Symposium. Los Alamitos: Institute of Electrical and Electronics Engineers, 2020. p. 1-10. ISBN: 978-1-7281-4312-5. Detail

  ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; SEKANINA, L.; VAŠÍČEK, Z.; VOJNAR, T. Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. APPLIED SOFT COMPUTING, 2020, vol. 95, no. 106466, p. 1-17. ISSN: 1568-4946. Detail

  GROCHOL, D.; SEKANINA, L. Evolutionary Design of Hash Functions for IPv6 Network Flow Hashing. In IEEE Congress on Evolutionary Computation. Los Alamitos: IEEE Computational Intelligence Society, 2020. p. 1-8. ISBN: 978-1-7281-6929-3. Detail

  HU, T.; NICOLAU, M.; SEKANINA, L. Special issue on highlights of genetic programming 2019 events. Genetic Programming and Evolvable Machines. 2020. p. 283-285. ISSN: 1389-2576. Detail

  HUSA, J.; SEKANINA, L. Evolving Cryptographic Boolean Functions with Minimal Multiplicative Complexity. In 2020 IEEE Congress on Evolutionary Computation (CEC). Los Alamitos: IEEE Computational Intelligence Society, 2020. p. 1-8. ISBN: 978-1-7281-6929-3. Detail

  MRÁZEK, V.; SEKANINA, L.; VAŠÍČEK, Z. Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2020, vol. 10, no. 4, p. 406-418. ISSN: 2156-3357. Detail

  MRÁZEK, V.; SEKANINA, L.; VAŠÍČEK, Z. Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. In 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems. Genoa: Institute of Electrical and Electronics Engineers, 2020. p. 243-247. ISBN: 978-1-7281-4922-6. Detail

  PRABAKARAN, B.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; SHAFIQUE, M. ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems. In 2020 57th ACM/IEEE Design Automation Conference (DAC). San Francisco: Institute of Electrical and Electronics Engineers, 2020. p. 1-6. ISBN: 978-1-4503-6725-7. Detail

  VAVERKA, F.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). Grenoble: Institute of Electrical and Electronics Engineers, 2020. p. 294-297. ISBN: 978-3-9819263-4-7. Detail

• 2019

  BADÁŇ, F.; SEKANINA, L. Optimizing Convolutional Neural Networks for Embedded Systems By Means of Neuroevolution. In Theory and Practice of Natural Computing. LNCS 11934. Cham: Springer International Publishing, 2019. p. 109-121. ISBN: 978-3-030-34499-3. Detail

  DRAHOŠOVÁ, M.; SEKANINA, L.; WIGLASZ, M. Adaptive Fitness Predictors in Coevolutionary Cartesian Genetic Programming. EVOLUTIONARY COMPUTATION, 2019, vol. 27, no. 3, p. 497-523. ISSN: 1063-6560. Detail

  KONČAL, O.; SEKANINA, L. Cartesian Genetic Programming as an Optimizer of Programs Evolved with Geometric Semantic Genetic Programming. In Genetic Programming 22nd European Conference, EuroGP 2019. Cham: Springer International Publishing, 2019. p. 98-113. ISBN: 978-3-030-16669-4. Detail

  MRÁZEK, V.; HANIF, M.; VAŠÍČEK, Z.; SEKANINA, L.; SHAFIQUE, M. autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. In The 56th Annual Design Automation Conference 2019 (DAC '19). Las Vegas: Association for Computing Machinery, 2019. p. 1-6. ISBN: 978-1-4503-6725-7. Detail

  MRÁZEK, V.; SEKANINA, L.; DOBAI, R.; SÝS, M.; ŠVENDA, P. Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. IEEE Trans. on VLSI Systems., 2019, vol. 27, no. 12, p. 2734-2744. ISSN: 1063-8210. Detail

  MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; HANIF, M.; SHAFIQUE, M. ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Denver: Institute of Electrical and Electronics Engineers, 2019. p. 1-8. ISBN: 978-1-7281-2350-9. Detail

  REK, P.; SEKANINA, L. TypeCNN: CNN Development Framework With Flexible Data Types. In Design, Automation and Test in Europe Conference. Florence: European Design and Automation Association, 2019. p. 292-295. ISBN: 978-3-9819263-2-3. Detail

  SEKANINA, L.; HU, T.; LOURENÇO, N.; RICHTER, H.; GARCÍA-SÁNCHEZ, P. Genetic Programming 22nd European Conference. Lecture Notes in Computer Science. Cham: Springer International Publishing, 2019. p. 0-0. ISBN: 978-3-030-16669-4. Detail

  SEKANINA, L.; VAŠÍČEK, Z.; MRÁZEK, V. Automated Search-Based Functional Approximation for Digital Circuits. In Approximate Circuits - Methodologies and CAD. Heidelberg: Springer International Publishing, 2019. p. 175-203. ISBN: 978-3-319-99322-5. Detail

  STAMENKOVIC, Z.; BOSIO, A.; CSEREY, G.; NOVÁK, O.; PLESKACZ, W.; SEKANINA, L.; STEININGER, A.; STOJANOVIC, G.; STOPJAKOVÁ, V. International Symposium on Design and Diagnostics of Electronic Circuits and Systems. In 2019 IEEE International Test Conference. Washington, DC: Institute of Electrical and Electronics Engineers, 2019. p. 1-4. ISBN: 978-1-7281-4823-6. Detail

  VAŠÍČEK, Z.; MRÁZEK, V.; SEKANINA, L. Automated Circuit Approximation Method Driven by Data Distribution. In Design, Automation and Test in Europe Conference. Florence: European Design and Automation Association, 2019. p. 96-101. ISBN: 978-3-9819263-2-3. Detail

• 2018

  CASTELLI, M.; SEKANINA, L.; ZHANG, M.; CAGNONI, S.; GARCÍA-SÁNCHEZ, P. 21st European Conference on Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2018. p. 0-0. ISBN: 978-3-319-77552-4. Detail

  ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; VOJNAR, T. ADAC: Automated Design of Approximate Circuits. In Proceedings of 30th International Conference on Computer Aided Verification (CAV'18). Oxford, UK: Springer International Publishing, 2018. p. 612-620. ISBN: 978-3-319-96145-3. Detail

  GROCHOL, D.; SEKANINA, L. Fast Reconfigurable Hash Functions for Network Flow Hashing in FPGAs. In Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems. Edinburgh: Institute of Electrical and Electronics Engineers, 2018. p. 257-263. ISBN: 978-1-5386-7753-7. Detail

  GROCHOL, D.; SEKANINA, L. Multi-Objective Evolution of Ultra-Fast General-Purpose Hash Functions. In European Conference on Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2018. p. 187-202. ISBN: 978-3-319-77553-1. Detail

  MRÁZEK, V.; SÝS, M.; VAŠÍČEK, Z.; SEKANINA, L.; MATYÁŠ, V. Evolving Boolean Functions for Fast and Efficient Randomness Testing. In Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '18). Kyoto: Association for Computing Machinery, 2018. p. 1302-1309. ISBN: 978-1-4503-5618-3. Detail

  MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. In Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems. Edinburgh: Institute of Electrical and Electronics Engineers, 2018. p. 264-271. ISBN: 978-1-5386-7753-7. Detail

  MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; JIANG, H.; HAN, J. Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. IEEE Trans. on VLSI Systems., 2018, vol. 26, no. 11, p. 2572-2576. ISSN: 1063-8210. Detail

  SEKANINA, L. Approximate Computing: An Old Job for Cartesian Genetic Programming?. In Inspired by Nature. Emergence, Complexity and Computation, Vol. 28. Cham: Springer International Publishing, 2018. p. 195-212. ISBN: 978-3-319-67996-9. Detail

  SEKANINA, L.; MRÁZEK, V.; VAŠÍČEK, Z. Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. In 25th IEEE International Conference on Electronics Circuits and Systems (ICECS). Bordeaux: IEEE Circuits and Systems Society, 2018. p. 377-380. ISBN: 978-1-5386-9562-3. Detail

  SEKANINA, L.; VAŠÍČEK, Z.; BOSIO, A.; TRAIOLA, M.; RECH, P.; OLIVEIRA, D.; FERNANDES, F.; DI CARLO, S. Special Session: How Approximate Computing impacts Verification, Test and Reliability. 2018 IEEE 36th VLSI Test Symposium. San Francisco: IEEE Computer Society, 2018. p. 0-0. ISBN: 978-1-5386-3774-6. Detail

  TREFZER, M.; SEKANINA, L. Guest Editorial: Bio-inspired Hardware and Evolvable Systems. IET Computers and Digital Techniques. 2018. p. 121-121. ISSN: 1751-8601. Detail

  WIGLASZ, M.; SEKANINA, L. Cooperative Coevolutionary Approximation in HOG-based Human Detection Embedded System. In 2018 IEEE Symposium Series on Computational Intelligence (SSCI 2018). Bengaluru: Institute of Electrical and Electronics Engineers, 2018. p. 1313-1320. ISBN: 978-1-5386-9276-9. Detail

• 2017

  ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; VOJNAR, T. Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished. In Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD). Irvine, CA: Institute of Electrical and Electronics Engineers, 2017. p. 416-423. ISBN: 978-1-5386-3093-8. Detail

  DOBAI, R.; KOŘENEK, J.; SEKANINA, L. Evolutionary design of hash function pairs for network filters. APPLIED SOFT COMPUTING, 2017, vol. 56, no. 7, p. 173-181. ISSN: 1568-4946. Detail

  GROCHOL, D.; SEKANINA, L. Comparison of Parallel Linear Genetic Programming Implementations. In Recent Advances in Soft Computing: Proceedings of the 22nd International Conference on Soft Computing (MENDEL 2016) held in Brno, Czech Republic, at June 8-10, 2016. Cham: Springer International Publishing, 2017. p. 64-76. ISBN: 978-3-319-58088-3. Detail

  GROCHOL, D.; SEKANINA, L. Multiobjective Evolution of Hash Functions for High Speed Networks. In Proceedings of the 2017 IEEE Congress on Evolutionary Computation. San Sebastian: IEEE Computer Society, 2017. p. 1533-1540. ISBN: 978-1-5090-4600-3. Detail

  KEŠNER, F.; SEKANINA, L.; BRÁZDIL, M. Modular Framework for Detection of Inter-ictal Spikes in iEEG. In The 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC'17). Los Alamos: Institute of Electrical and Electronics Engineers, 2017. p. 418-421. ISBN: 978-1-5090-2809-2. Detail

  MCDERMOTT, J.; CASTELLI, M.; SEKANINA, L.; HAASDIJK, E.; GARCÍA-SÁNCHEZ, P. 20th European Conference on Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2017. p. 0-0. ISBN: 978-3-319-55696-3. Detail

  MINAŘÍK, M.; SEKANINA, L. On Evolutionary Approximation of Sigmoid Function for HW/SW Embedded Systems. In 20th European Conference on Genetic Programming, EuroGP 2017. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2017. p. 343-358. ISBN: 978-3-319-55696-3. Detail

  MRÁZEK, V.; HRBÁČEK, R.; VAŠÍČEK, Z.; SEKANINA, L. EvoApprox8b: Library of Approximate Adders and Multipliers for Circuit Design and Benchmarking of Approximation Methods. In Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017. p. 258-261. ISBN: 978-3-9815370-9-3. Detail

  SEKANINA, L.; VAŠÍČEK, Z.; MRÁZEK, V. Approximate Circuits in Low-Power Image and Video Processing: The Approximate Median Filter. Radioengineering, 2017, vol. 26, no. 3, p. 623-632. ISSN: 1210-2512. Detail

  SHAFIQUE, M.; HAFIZ, R.; JAVED, M.; ABBAS, S.; SEKANINA, L.; VAŠÍČEK, Z.; MRÁZEK, V. Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. In 2017 IEEE Computer Society Annual Symposium on VLSI. Los Alamitos: IEEE Computer Society Press, 2017. p. 627-632. ISBN: 978-1-5090-6762-6. Detail

  VAŠÍČEK, Z.; MRÁZEK, V.; SEKANINA, L. Towards Low Power Approximate DCT Architecture for HEVC Standard. In Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017. p. 1576-1581. ISBN: 978-3-9815370-9-3. Detail

  WIGLASZ, M.; SEKANINA, L. Evolutionary Approximation of Gradient Orientation Module in HOG-based Human Detection System. In 2017 IEEE Global Conference on Signal and Information Processing GlobalSIP 2017. Montreal: IEEE Signal Processing Society, 2017. p. 1300-1304. ISBN: 978-1-5090-5989-8. Detail

• 2016

  DOBAI, R.; KOŘENEK, J.; SEKANINA, L. Adaptive Development of Hash Functions in FPGA-Based Network Routers. In 2016 IEEE Symposium Series on Computational Intelligence. Athens: IEEE Computational Intelligence Society, 2016. p. 1-8. ISBN: 978-1-5090-4240-1. Detail

  DVOŘÁČEK, P.; SEKANINA, L. Evolutionary Approximation of Edge Detection Circuits. In 19th European Conference on Genetic programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2016. p. 19-34. ISBN: 978-3-319-30667-4. Detail

  GROCHOL, D.; SEKANINA, L. Evolutionary Design of Fast High-quality Hash Functions for Network Applications. In GECCO '16 Proceedings of the 2016 on Genetic and Evolutionary Computation Conference. New York, NY: Association for Computing Machinery, 2016. p. 901-908. ISBN: 978-1-4503-4206-3. Detail

  GROCHOL, D.; SEKANINA, L.; KOŘENEK, J.; ŽÁDNÍK, M.; KOŠAŘ, V. Evolutionary Circuit Design for Fast FPGA-Based Classification of Network Application Protocols. APPLIED SOFT COMPUTING, 2016, vol. 38, no. 1, p. 933-941. ISSN: 1568-4946. Detail

  HOLÍK, L.; LENGÁL, O.; ROGALEWICZ, A.; SEKANINA, L.; VAŠÍČEK, Z.; VOJNAR, T. Towards Formal Relaxed Equivalence Checking in Approximate Computing Methodology. 2nd Workshop on Approximate Computing (WAPCO 2016). Prague: 2016. p. 1-6. Detail

  MRÁZEK, V.; SARWAR, S.; SEKANINA, L.; VAŠÍČEK, Z.; ROY, K. Design of Power-Efficient Approximate Multipliers for Approximate Artificial Neural Networks. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Austin, TX: Association for Computing Machinery, 2016. p. 811-817. ISBN: 978-1-4503-4466-1. Detail

  SÁNCHEZ-CLEMENTE, A.; ENTRENA, L.; HRBÁČEK, R.; SEKANINA, L. Error Mitigation using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches. IEEE TRANSACTIONS ON RELIABILITY, 2016, vol. 65, no. 4, p. 1871-1883. ISSN: 0018-9529. Detail

  SEKANINA, L. Introduction to Approximate Computing: Embedded Tutorial. In 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Košice: Institute of Electrical and Electronics Engineers, 2016. p. 90-95. ISBN: 978-1-5090-2467-4. Detail

  SEKANINA, L.; KAPUSTA, V. Visualisation and Analysis of Genetic Records Produced by Cartesian Genetic Programming. In GECCO'16 Companion. New York: Association for Computing Machinery, 2016. p. 1411-1418. ISBN: 978-1-4503-4323-7. Detail

  SEKANINA, L.; VAŠÍČEK, Z. Genetic Improvement for Approximate Computing. 2nd Workshop on Approximate Computing (WAPCO 2016). Prague: 2016. p. 1-2. Detail

  VAŠÍČEK, Z.; MRÁZEK, V.; SEKANINA, L. Evolutionary Functional Approximation of Circuits Implemented into FPGAs. In 2016 IEEE Symposium Series on Computational Intelligence. Athens: Institute of Electrical and Electronics Engineers, 2016. p. 1-8. ISBN: 978-1-5090-4240-1. Detail

  VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Design of Complex Approximate Combinational Circuits. Genetic Programming and Evolvable Machines, 2016, vol. 17, no. 2, p. 169-192. ISSN: 1389-2576. Detail

  VAŠÍČEK, Z.; SEKANINA, L. Search-based synthesis of approximate circuits implemented into FPGAs. In 26th International Conference on Field Programmable Logic and Applications. Lausanne: Institute of Electrical and Electronics Engineers, 2016. p. 1-4. ISBN: 978-2-8399-1844-2. Detail

  VAVERKA, F.; HRBÁČEK, R.; SEKANINA, L. Evolving Component Library for Approximate High Level Synthesis. In 2016 IEEE Symposium Series on Computational Intelligence. Athens: IEEE Computational Intelligence Society, 2016. p. 1-8. ISBN: 978-1-5090-4240-1. Detail

• 2015

  DOBAI, R.; SEKANINA, L. Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware. ACM Transactions on Reconfigurable Technology and Systems, 2015, vol. 8, no. 3, p. 1-24. ISSN: 1936-7406. Detail

  DRAHOŠOVÁ, M.; HULVA, J.; SEKANINA, L. Indirectly Encoded Fitness Predictors Coevolved with Cartesian Programs. In Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2015. p. 113-125. ISBN: 978-3-319-16500-4. Detail

  GROCHOL, D.; SEKANINA, L.; ŽÁDNÍK, M.; KOŘENEK, J. A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP. In Applications of Evolutionary Computation, 18th European Conference. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2015. p. 67-78. ISBN: 978-3-319-16548-6. Detail

  KEŠNER, F.; CIMBÁLNÍK, J.; DOLEŽALOVÁ, I.; BRÁZDIL, M.; SEKANINA, L. Fast Automated Interictal Spike Detection in iEEG/ECoG Recordings. Proceedings of NEUROTECHNIX: International Congress on Neurotechnology, Electronics and Informatics. Lisabon: 2015. p. 1-4. Detail

  MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Approximation of Software for Embedded Systems: Median Function. In GECCO Companion '15 Proceedings of the Companion Publication of the 2015 on Genetic and Evolutionary Computation Conference. ACM. New York: Association for Computing Machinery, 2015. p. 795-801. ISBN: 978-1-4503-3488-4. Detail

  PETRLÍK, J.; SEKANINA, L. Towards Robust and Accurate Traffic Prediction Using Parallel Multiobjective Genetic Algorithms and Support Vector Regression. In 2015 IEEE 18th International Conference on Intelligent Transportation Systems. Los Alamitos: IEEE Computer Society, 2015. p. 2231-2236. ISBN: 978-1-4673-6596-3. Detail

  SEKANINA, L. Principles and Applications of Polymorphic Circuits. In Evolvable Hardware - From Practice to Application. Berlin: Springer Verlag, 2015. p. 209-224. ISBN: 978-3-662-44615-7. Detail

  SEKANINA, L.; VAŠÍČEK, Z. Evolutionary Computing in Approximate Circuit Design and Optimization. 1st Workshop on Approximate Computing (WAPCO 2015). Amsterdam: 2015. p. 1-6. Detail

  SEKANINA, L.; VAŠÍČEK, Z. Functional Equivalence Checking for Evolution of Complex Digital Circuits. In Evolvable Hardware - From Practice to Application. Berlin: Springer Verlag, 2015. p. 175-189. ISBN: 978-3-662-44615-7. Detail

  VAŠÍČEK, Z.; SEKANINA, L. Circuit Approximation Using Single- and Multi-Objective Cartesian GP. In Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2015. p. 217-229. ISBN: 978-3-319-16500-4. Detail

  VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Approach to Approximate Digital Circuits Design. IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, 2015, vol. 19, no. 3, p. 432-444. ISSN: 1089-778X. Detail

  VAŠÍČEK, Z.; SEKANINA, L. Evolutionary approximation of complex digital circuits. In Proceedings of the Companion Publication of the 2015 on Genetic and Evolutionary Computation Conference. New York: Association for Computing Machinery, 2015. p. 1505-1506. ISBN: 978-1-4503-3488-4. Detail

• 2014

  DOBAI, R.; GLETTE, K.; TORRESEN, J.; SEKANINA, L. Evolutionary Digital Circuit Design with Fast Candidate Solution Establishment in Field Programmable Gate Arrays. In 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014. p. 85-92. ISBN: 978-1-4799-4480-4. Detail

  DRAHOŠOVÁ, M.; KOMJÁTHY, G.; SEKANINA, L. Towards Compositional Coevolution in Evolutionary Circuit Design. In 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014. p. 157-164. ISBN: 978-1-4799-4479-8. Detail

  HRBÁČEK, R.; SEKANINA, L. Towards Highly Optimized Cartesian Genetic Programming: From Sequential via SIMD and Thread to Massive Parallel Implementation. In GECCO '14 Proceedings of the 2014 conference on Genetic and evolutionary computation. New York: Association for Computing Machinery, 2014. p. 1015-1022. ISBN: 978-1-4503-2662-9. Detail

  MINAŘÍK, M.; SEKANINA, L. Exploring the Search Space of Hardware / Software Embedded Systems by Means of GP. In Genetic Programming, 17th European Conference, EuroGP 2014. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2014. p. 112-123. ISBN: 978-3-662-44302-6. Detail

  PETRLÍK, J.; FUČÍK, O.; SEKANINA, L. Multiobjective Selection of Input Sensors for SVR Applied to Road Traffic Prediction. In Parallel Problem Solving from Nature - PPSN XIII. Lecture Notes in Computer Science. Heidelberg: Springer Verlag, 2014. p. 802-811. ISBN: 978-3-319-10761-5. Detail

  PETRLÍK, J.; FUČÍK, O.; SEKANINA, L. Multiobjective Selection of Input Sensors for Travel Times Forecasting Using Support Vector Regression. In 2014 IEEE Symposium on Computational Intelligence in Vehicles and Transportation Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014. p. 14-21. ISBN: 978-1-4799-4498-9. Detail

  SEKANINA, L.; PTÁK, O.; VAŠÍČEK, Z. Cartesian Genetic Programming as Local Optimizer of Logic Networks. In 2014 IEEE Congress on Evolutionary Computation. Beijing: IEEE Computational Intelligence Society, 2014. p. 2901-2908. ISBN: 978-1-4799-1488-3. Detail

  SEKANINA, L.; VAŠÍČEK, Z. On Evolutionary Approximation of Logic Circuits. In Computing with New Resources. Berlin: Springer Verlag, 2014. p. 367-378. ISBN: 978-3-319-13349-2. Detail

  VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Design of Approximate Multipliers Under Different Error Metrics. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warsaw: IEEE Computer Society, 2014. p. 135-140. ISBN: 978-1-4799-4558-0. Detail

  VAŠÍČEK, Z.; SEKANINA, L. How to Evolve Complex Combinational Circuits From Scratch?. In 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014. p. 133-140. ISBN: 978-1-4799-4480-4. Detail

• 2013

  DOBAI, R.; SEKANINA, L. Image Filter Evolution on the Xilinx Zynq Platform. Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems. Torino: IEEE Circuits and Systems Society, 2013. p. 164-171. ISBN: 978-1-4673-6381-5. Detail

  DOBAI, R.; SEKANINA, L. Towards Evolvable Systems Based on the Xilinx Zynq Platform. 2013 IEEE International Conference on Evolvable Systems (ICES). Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI). Singapur: IEEE Computational Intelligence Society, 2013. p. 89-95. ISBN: 978-1-4673-5869-9. Detail

  KORČEK, P.; SEKANINA, L.; FUČÍK, O. Advanced Approach to Calibration of Traffic Microsimulation Models using Travel Times. Journal of Cellular Automata, 2013, vol. 8, no. 6, p. 457-467. ISSN: 1557-5969. Detail

  MINAŘÍK, M.; SEKANINA, L. Concurrent Evolution of Hardware and Software for Application-Specific Microprogrammed Systems. 2013 IEEE International Conference on Evolvable Systems (ICES). Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI). Singapur: IEEE Computational Intelligence Society, 2013. p. 43-50. ISBN: 978-1-4673-5869-9. Detail

  PETRLÍK, J.; SEKANINA, L. Multiobjective evolution of approximate multiple constant multipliers. In IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013. Brno: IEEE Computer Society, 2013. p. 116-119. ISBN: 978-1-4673-6133-0. Detail

  SALVADOR, R.; OTERO, A.; MORA, J.; DE LA TORRE, E.; RIESGO, T.; SEKANINA, L. Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. IEEE TRANSACTIONS ON COMPUTERS, 2013, vol. 62, no. 8, p. 1481-1493. ISSN: 0018-9340. Detail

  SEKANINA, L. Ubiquity symposium: Evolutionary computation and the processes of life: evolutionary computation in physical world. Ubiquity, 2013, vol. 2013, no. 2, p. 1-7. ISSN: 1530-2180. Detail

  SEKANINA, L.; RŮŽIČKA, R.; VAŠÍČEK, Z.; ŠIMEK, V.; HANÁČEK, P. Implementing a Unique Chip ID on a Reconfigurable Polymorphic Circuit. Information Technology and Control, 2013, vol. 42, no. 1, p. 7-14. ISSN: 1392-124X. Detail

  SEKANINA, L.; VAŠÍČEK, Z. Approximate Circuit Design by Means of Evolvable Hardware. In 2013 IEEE International Conference on Evolvable Systems (ICES). Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI). Singapur: IEEE Computer Society, 2013. p. 21-28. ISBN: 978-1-4673-5847-7. Detail

  VAŠÍČEK, Z.; BIDLO, M.; SEKANINA, L. Evolution of efficient real-time non-linear image filters for FPGAs. SOFT COMPUTING, 2013, vol. 17, no. 11, p. 2163-2180. ISSN: 1432-7643. Detail

• 2012

  DRAHOŠOVÁ, M.; SEKANINA, L. Coevolution in Cartesian Genetic Programming. Proc. of the 15th European Conference on Genetic Programming. Lecture Notes in Computer Science. Heidelberg: Springer Verlag, 2012. p. 182-193. ISBN: 978-3-642-29138-8. Detail

  DRAHOŠOVÁ, M.; SEKANINA, L. Acceleration of Evolutionary Image Filter Design Using Coevolution in Cartesian GP. Lecture Notes in Computer Science, 2012, vol. 2012, no. 7491, p. 163-172. ISSN: 0302-9743. Detail

  KORČEK, P.; SEKANINA, L.; FUČÍK, O. Calibrating Traffic Simulation Model using Vehicle Travel Times. Lecture Notes in Computer Science, 2012, vol. 2012, no. 7495, p. 807-816. ISSN: 0302-9743. Detail

  KORČEK, P.; SEKANINA, L.; FUČÍK, O. Evolutionary approach to calibration of cellular automaton based traffic simulation model. In Proceedings of the 15th International IEEE Conference on Intelligent Transportation Systems. Anchorage: IEEE Intelligent Transportation Systems Society, 2012. p. 122-129. ISBN: 978-1-4673-3062-6. Detail

  PETRLÍK, J.; KORČEK, P.; FUČÍK, O.; BESZÉDEŠ, M.; SEKANINA, L. Estimation of traffic density map using evolutionary algorithm. In Proceedings of the 15th International IEEE Conference on Intelligent Transportation Systems. Anchorage: IEEE Intelligent Transportation Systems Society, 2012. p. 632-637. ISBN: 978-1-4673-3062-6. Detail

  PETRLÍK, J.; SEKANINA, L. Multiobjective Evolution of Multiple-Constant Multipliers. Proceedings of the 18th International Conference on Soft Computing (MENDEL2012). Brno: Faculty of Mechanical Engineering BUT, 2012. p. 64-69. ISBN: 978-80-214-4540-6. Detail

  SALVADOR, R.; OTERO, A.; MORA, J.; DE LA TORRE, E.; RIESGO, T.; SEKANINA, L. Implementation Techniques for Evolvable HW Systems: Virtual vs. Dynamic Reconfiguration. Proc. of the 22nd International Conference on Field Programmable Logic and Applications (FPL). Oslo: IEEE Computer Society, 2012. p. 547-550. ISBN: 978-1-4673-2257-7. Detail

  SALVADOR, R.; VIDAL, A.; MORENO, F.; RIESGO, T.; SEKANINA, L. Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling. Microprocessors and Microsystems, 2012, vol. 36, no. 5, p. 427-438. ISSN: 0141-9331. Detail

  SEKANINA, L. Evolvable hardware. In Handbook of Natural Computing. Berlin: Springer Verlag, 2012. p. 1657-1705. ISBN: 978-3-540-92909-3. Detail

  SEKANINA, L.; SALAJKA, V. Towards New Applications of Multi-Function Logic: Image Multi-Filtering. Proc. of the 2012 Design, Automation and Test in Europe. Dresden: European Design and Automation Association, 2012. p. 824-827. ISBN: 978-1-4577-2145-8. Detail

  SEKANINA, L.; SALAJKA, V.; VAŠÍČEK, Z. Two-Step Evolution of Polymorphic Circuits for Image Multi-Filtering. In 2012 IEEE World Congress on Computational Intelligence. CA: Institute of Electrical and Electronics Engineers, 2012. p. 432-439. ISBN: 978-1-4673-1508-1. Detail

  SEKANINA, L.; VAŠÍČEK, Z. A SAT-based Fitness Function for Evolutionary Optimization of Polymorphic Circuits. Proc. of the 2012 Design, Automation and Test in Europe. Dresden: European Design and Automation Association, 2012. p. 715-720. ISBN: 978-1-4577-2145-8. Detail

  SMOLKA, T.; ŠVENDA, P.; SEKANINA, L.; MATYÁŠ, V. Evolutionary Design of Message Efficient Secrecy Amplification Protocols. Proc. of the 15th European Conference on Genetic Programming. Lecture Notes in Computer Science. Heidelberg: Springer Verlag, 2012. p. 194-205. ISBN: 978-3-642-29138-8. Detail

  VAŠÍČEK, Z.; SEKANINA, L. On Area Minimization of Complex Combinational Circuits Using Cartesian Genetic Programming. In 2012 IEEE World Congress on Computational Intelligence. CA: Institute of Electrical and Electronics Engineers, 2012. p. 2379-2386. ISBN: 978-1-4673-1508-1. Detail

  ŽALOUDEK, L.; SEKANINA, L. Cellular automata-based systems with fault-tolerance. Natural Computing, 2012, vol. 11, no. 4, p. 673-685. ISSN: 1567-7818. Detail

• 2011

  GAJDA, Z.; SEKANINA, L. Recent Advances in Evolutionary Synthesis and Optimization of Ordinary and Polymorphic Circuits. Brno: Faculty of Information Technology BUT, 2011. 111 p. ISBN: 978-80-214-4417-1. Detail

  GAJDA, Z.; SEKANINA, L. On Evolutionary Synthesis of Compact Polymorphic Combinational Circuits. JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING, 2011, vol. 17, no. 6, p. 607-631. ISSN: 1542-3980. Detail

  KORČEK, P.; SEKANINA, L.; FUČÍK, O. A Scalable Cellular Automata Based Microscopic Traffic Simulation. Proceedings of the IEEE Intelligent Vehicles Symposium 2011 (IV11). Baden-Baden: IEEE Intelligent Transportation Systems Society, 2011. p. 13-18. ISBN: 978-1-4577-0889-3. Detail

  KORČEK, P.; SEKANINA, L.; FUČÍK, O. Cellular automata based traffic simulation accelerated on GPU. Proceedings of the 17th International Conference on Soft Computing (MENDEL2011). Brno: Institute of Automation and Computer Science FME BUT, 2011. p. 395-402. ISBN: 978-80-214-4302-0. Detail

  KORČEK, P.; SEKANINA, L.; FUČÍK, O. Microscopic traffic simulation using CUDA. Advanced Computer Architecture and Compilation for High-Performace and Embedded Systems (ACACES 2011) Poster Abstracts. Fiuggi: Academia Press, 2011. p. 207-210. ISBN: 978-90-382-1798-7. Detail

  MINAŘÍK, M.; SEKANINA, L. Evolution of Iterative Formulas Using Cartesian Genetic Programming. Lecture Notes in Computer Science, 2011, vol. 2011, no. 6881, p. 11-20. ISSN: 0302-9743. Detail

  OTERO, A.; SALVADOR, R.; MORA, J.; DE LA TORRE, E.; RIESGO, T.; SEKANINA, L. A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self-Adaptive Systems. Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2011. p. 336-343. ISBN: 978-1-4577-0599-1. Detail

  RŮŽIČKA, R.; ŠIMEK, V.; SEKANINA, L. Behavior of CMOS Polymorphic Circuits in High Temperature Environment. Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Cottbus: IEEE Computer Society, 2011. p. 447-452. ISBN: 978-1-4244-9753-9. Detail

  SALVADOR, R.; MORENO, F.; RIESGO, T.; SEKANINA, L. Evolutionary Approach to Improve Wavelet Transforms for Image Compression in Embedded Systems. EURASIP Journal on Advances in Signal Processing, 2011, vol. 2011, no. 2011, p. 1-20. ISSN: 1687-6172. Detail

  SALVADOR, R.; OTERO, A.; MORA, J.; DE LA TORRE, E.; RIESGO, T.; SEKANINA, L. Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2011. p. 184-191. ISBN: 978-1-4577-0599-1. Detail

  SALVADOR, R.; OTERO, A.; MORA, J.; DE LA TORRE, E.; SEKANINA, L.; RIESGO, T. Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. Proc. of the 2011 International Conference on ReConFigurable Computing and FPGAs. Los Alamitos: IEEE Computer Society, 2011. p. 164-169. ISBN: 978-0-7695-4551-6. Detail

  SALVADOR, R.; VIDAL, A.; MORENO, F.; RIESGO, T.; SEKANINA, L. Bio-inspired FPGA architecture for self-calibration of an image compression core based on wavelet transforms in embedded systems. VLSI Circuits and Systems V. Proc. of SPIE Vol. 8067. Bellingham: SPIE - the international society for optics and photonics, 2011. p. 1-13. ISBN: 978-0-8194-8656-1. Detail

  SEKANINA, L. Evolution of digital circuits. Proceedings of the 2011 GECCO conference companion on Genetic and evolutionary computation. New York: Association for Computing Machinery, 2011. p. 1343-1359. ISBN: 978-1-4503-0690-4. Detail

  SEKANINA, L. Evolutionary hardware design (Invited Paper). VLSI Circuits and Systems V. Proc. of SPIE Vol. 8067. Bellingham: SPIE - the international society for optics and photonics, 2011. p. 1-11. ISBN: 978-0-8194-8656-1. Detail

  SEKANINA, L.; HARDING, S.; BANZHAF, W.; KOWALIW, T. Image Processing and CGP. In Cartesian Genetic Programming. Natural Computing Series. Berlin: Springer Verlag, 2011. p. 181-215. ISBN: 978-3-642-17309-7. Detail

  SEKANINA, L.; KOMENDA, T. Global Control in Polymorphic Cellular Automata. Journal of Cellular Automata, 2011, vol. 6, no. 4, p. 301-321. ISSN: 1557-5969. Detail

  SEKANINA, L.; VAŠÍČEK, Z. CGP Acceleration Using Field-Programmable Gate Arrays. In Cartesian Genetic Programming. Natural Computing Series. Berlin: Springer Verlag, 2011. p. 217-230. ISBN: 978-3-642-17309-7. Detail

  SEKANINA, L.; WALKER, J.; KAUFMANN, P.; PLATZNER, M. Evolution of Electronic Circuits. In Cartesian Genetic Programming. Natural Computing Series. Berlin: Springer Verlag, 2011. p. 125-179. ISBN: 978-3-642-17309-7. Detail

  VAŠÍČEK, Z.; BIDLO, M.; SEKANINA, L.; GLETTE, K. Evolutionary Design of Efficient and Robust Switching Image Filters. In Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2011. p. 192-199. ISBN: 978-1-4577-0599-1. Detail

  VAŠÍČEK, Z.; SEKANINA, L. A Global Postsynthesis Optimization Method for Combinational Circuits. Proc. of the Design, Automation and Test in Europe DATE 2011. Grenoble: European Design and Automation Association, 2011. p. 1525-1528. ISBN: 978-3-9810801-7-9. Detail

  VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Optimization of Complex Digital Circuits. 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2011. p. 127-127. ISBN: 978-80-214-4305-1. Detail

  VAŠÍČEK, Z.; SEKANINA, L. Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. Genetic Programming and Evolvable Machines, 2011, vol. 12, no. 3, p. 305-327. ISSN: 1389-2576. Detail

  ŽALOUDEK, L.; SEKANINA, L. Increasing Fault-Tolerance in Cellular-Based Systems. Lecture Notes in Computer Science, 2011, vol. 2011, no. 6714, p. 234-245. ISSN: 0302-9743. Detail

• 2010

  BIDLO, M.; SEKANINA, L. On Impact of Environment on the Complexity Generated by Evolutionary Development. In MENDEL 2010 - 16th International Conference on Soft Computing. Brno: Faculty of Mechanical Engineering BUT, 2010. p. 501-508. ISBN: 978-80-214-4120-0. Detail

  FIŠER, P.; SCHMIDT, J.; VAŠÍČEK, Z.; SEKANINA, L. On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming. Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010. p. 346-351. ISBN: 978-1-4244-6610-8. Detail

  GAJDA, Z.; SEKANINA, L. An Efficient Selection Strategy for Digital Circuit Evolution. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2010. p. 13-24. ISBN: 978-3-642-15322-8. Detail

  GAJDA, Z.; SEKANINA, L. When Does Cartesian Genetic Programming Minimize the Phenotype Size Implicitly?. Proceeding of Genetic and Evolutionary Computation Conference, GECCO 2010. New York: Association for Computing Machinery, 2010. p. 983-984. ISBN: 978-1-4503-0072-8. Detail

  KORČEK, P.; SEKANINA, L.; FUČÍK, O. Towards Scalable and Accurate Microscopic Traffic Simulation Using Advanced Cellular Automata Based Models. Proceedings of the 13th International IEEE Conference on Intelligent Transportation Systems Workshops. Madeira Island: IEEE Intelligent Transportation Systems Society, 2010. p. 27-35. ISBN: 978-972-8822-20-0. Detail

  SALVADOR, R.; MORENO, F.; RIESGO, T.; SEKANINA, L. Evolutionary design and optimization of Wavelet Transforms for image compression in embedded systems. Proc. of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2010. p. 177-184. ISBN: 978-1-4244-5888-2. Detail

  SALVADOR, R.; MORENO, F.; RIESGO, T.; SEKANINA, L. High level validation of an optimization algorithm for the implementation of adaptive Wavelet Transforms in FPGAs. Proc. of 13th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2010. p. 96-103. ISBN: 978-0-7695-4171-6. Detail

  SALVADOR, R.; MORENO, F.; RIESGO, T.; SEKANINA, L. Implementation of bio-inspired adaptive wavelet transforms in FPGAs. Modelling, validation and profiling of the algorithm. Proceedings of the XXV Conference on Design of Circuits and Integrated Systems. Lanzarote: The Universidad de Las Palmas de Gran Canaria, 2010. p. 210-215. ISBN: 978-84-693-7393-4. Detail

  SEKANINA, L. Evoluční návrh elektronických obvodů. Automa, 2010, roč. 2010, č. 1, s. 48-51. ISSN: 1210-9592. Detail

  SEKANINA, L. Evoluční návrh hardware. In Umelá inteligencia a kognitívna veda II. Edícia výskumných textov FIIT STU. Bratislava: Vydavateľstvo STU, 2010. s. 437-465. ISBN: 978-80-227-3284-0. Detail

  ŠIMÁČEK, J.; SEKANINA, L.; STAREČEK, L. Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2010. p. 214-225. ISBN: 978-3-642-15322-8. Detail

  ŠIMEK, V.; RŮŽIČKA, R.; SEKANINA, L. On Analysis of Fabricated Polymorphic Circuits. Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010. p. 281-284. ISBN: 978-1-4244-6610-8. Detail

  VAŠÍČEK, Z.; SEKANINA, L. Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units. Computing and Informatics, 2010, vol. 29, no. 6, p. 1359-1371. ISSN: 1335-9150. Detail

  VAŠÍČEK, Z.; SEKANINA, L.; BIDLO, M. A Method for Design of Impulse Bursts Noise Filters Optimized for FPGA Implementations. DATE 2010: Design, Automation and Test in Europe. Dresden: European Design and Automation Association, 2010. p. 1731-1736. ISBN: 978-3-9810801-6-2. Detail

  ŽALOUDEK, L.; SEKANINA, L.; ŠIMEK, V. Accelerating Cellular Automata Evolution on Graphics Processing Units. International Journal on Advances in Software, 2010, vol. 3, no. 1, p. 294-303. ISSN: 1942-2628. Detail

• 2009

  GAJDA, Z.; SEKANINA, L. Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming. Proc. of 2009 IEEE Congress on Evolutionary Computation. NA: IEEE Computational Intelligence Society, 2009. p. 1599-1604. ISBN: 978-1-4244-2958-5. Detail

  NEGOITA, M.; SEKANINA, L.; STOICA, A. Adaptive and evolvable hardware and systems: the state of the art and the prospectus for future development. Journal of Automation, Mobile Robotics and Intelligent Systems, 2009, vol. 3, no. 2, p. 70-75. ISSN: 1897-8649. Detail

  SEKANINA, L. Evolvable Hardware: From Applications to Implications for the Theory of Computation. Proc. of the 8th Int. Conference on Unconventional Computation. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2009. p. 24-36. ISBN: 978-3-642-03744-3. Detail

  SEKANINA, L.; RŮŽIČKA, R.; GAJDA, Z. Polymorphic FIR Filters with Backup Mode Enabling Power Savings. Proc. of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2009. p. 43-50. ISBN: 978-0-7695-3714-6. Detail

  SEKANINA, L.; RŮŽIČKA, R.; VAŠÍČEK, Z.; PROKOP, R.; FUJCIK, L. REPOMO32 - New Reconfigurable Polymorphic Integrated Circuit for Adaptive Hardware. Proc. of the 2009 IEEE Symposium Series on Computational Intelligence - Workshop on Evolvable and Adaptive Hardware. Nashville: IEEE Computational Intelligence Society, 2009. p. 39-46. ISBN: 978-1-4244-2755-0. Detail

  SEKANINA, L.; VAŠÍČEK, Z.; RŮŽIČKA, R.; BIDLO, M.; JAROŠ, J.; ŠVENDA, P. Evoluční hardware: Od automatického generování patentovatelných invencí k sebemodifikujícím se strojům. Edice Gerstner. Edice Gerstner. Praha: Nakladatelství Academia, 2009. 328 s. ISBN: 978-80-200-1729-1. Detail

  ŠVENDA, P.; SEKANINA, L.; MATYÁŠ, V. Evolutionary Design of Secrecy Amplification Protocols for Wireless Sensor Networks. Proc. of the ACM Conference on Wireless Network Security. New York: Association for Computing Machinery, 2009. p. 225-236. ISBN: 978-1-60558-460-7. Detail

  VAŠÍČEK, Z.; BIDLO, M.; SEKANINA, L.; TORRESEN, J.; GLETTE, K.; FURUHOLMEN, M. Evolution of Impulse Bursts Noise Filters. Proc. of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2009. p. 27-34. ISBN: 978-0-7695-3714-6. Detail

  VAŠÍČEK, Z.; SEKANINA, L. Efficient Hardware Accelerator for Symbolic Regression Problems. 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2009. p. 192-199. ISBN: 978-80-87342-04-6. Detail

  ŽALOUDEK, L.; SEKANINA, L.; ŠIMEK, V. GPU Accelerators for Evolvable Cellular Automata. Computation World: Future Computing, Service Computation, Adaptive, Content, Cognitive, Patterns. Athens: Institute of Electrical and Electronics Engineers, 2009. p. 533-537. ISBN: 978-0-7695-3862-4. Detail

• 2008

  HORNBY, G.; SEKANINA, L.; HADDOW, P. Proceedings of Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. p. 0-0. ISBN: 978-3-540-85856-0. Detail

  NEGOITA, M.; SEKANINA, L.; STOICA, A. Adaptive and Evolvable Hardware and Systems: The State of the Art and the Prospectus for Future Development. Knowledge-Based Intelligent Information and Engineering Systems. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. p. 310-318. ISBN: 978-3-540-85566-8. Detail

  PEČENKA, T.; SEKANINA, L.; KOTÁSEK, Z. Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2008, vol. 13, no. 3, p. 1-21. ISSN: 1084-4309. Detail

  RŮŽIČKA, R.; SEKANINA, L.; PROKOP, R. Physical Demonstration of Polymorphic Self-checking Circuits. Proc. of the 14th IEEE Int. On-Line Testing Symposium. Los Alamitos: IEEE Computer Society, 2008. p. 31-36. ISBN: 978-0-7695-3264-6. Detail

  SEKANINA, L.; MIKUŠEK, P. Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures. Applications of Evolutionary Computing. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. p. 144-153. ISBN: 978-3-540-78760-0. Detail

  SEKANINA, L.; STAREČEK, L.; KOTÁSEK, Z.; GAJDA, Z. Polymorphic Gates in Design and Test of Digital Circuits. International Journal of Unconventional Computing, 2008, vol. 4, no. 2, p. 125-142. ISSN: 1548-7199. Detail

  STAREČEK, L.; SEKANINA, L.; KOTÁSEK, Z. Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008. p. 255-258. ISBN: 978-1-4244-2276-0. Detail

  VAŠÍČEK, Z.; ČAPKA, L.; SEKANINA, L. Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit. Proc. of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2008. p. 3-10. ISBN: 978-0-7695-3166-3. Detail

  VAŠÍČEK, Z.; SEKANINA, L. Hardware Accelerators for Cartesian Genetic Programming. Eleventh European Conference on Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. p. 230-241. ISBN: 978-3-540-78670-2. Detail

  VAŠÍČEK, Z.; SEKANINA, L. Novel Hardware Implementation of Adaptive Median Filters. In Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008. p. 110-115. ISBN: 978-1-4244-2276-0. Detail

  VAŠÍČEK, Z.; ŽÁDNÍK, M.; SEKANINA, L.; TOBOLA, J. On Evolutionary Synthesis of Linear Transforms. Evolvable Systems: From Biology > to > Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. p. 141-152. ISBN: 978-3-540-85856-0. Detail

  ŽALOUDEK, L.; SEKANINA, L. Transistor-level Evolution of Digital Circuits Using a Special Circuit Simulator. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. p. 320-331. ISBN: 978-3-540-85856-0. Detail

• 2007

  SEKANINA, L. Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates. 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Gliwice: IEEE Computer Society, 2007. p. 243-246. ISBN: 1424411610. Detail

  SEKANINA, L. Evolution of Polymorphic Self-Checking Circuits. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2007. p. 186-197. ISBN: 978-3-540-74625-6. Detail

  SEKANINA, L. Vztah mezi abstraktním a fyzickým výpočtem v kontextu evolučního návrhu. Kognice a umělý život VII. Opava: Slezská univerzita v Opavě, 2007. s. 305-310. ISBN: 9788072484126. Detail

  SEKANINA, L. Evolutionary Functional Recovery in Virtual Reconfigurable Circuits. ACM Journal on Emerging Technologies in Computing Systems, 2007, vol. 3, no. 2, p. 1-22. ISSN: 1550-4832. Detail

  SEKANINA, L. Evolved Computing Devices and the Implementation Problem. MINDS AND MACHINES, 2007, vol. 17, no. 3, p. 311-329. ISSN: 0924-6495. Detail

  SEKANINA, L.; MARTÍNEK, T. Evolving Image Operators Directly in Hardware. In Genetic and Evolutionary Computation for Image Processing and Analysis. EURASIP Book Series on Signal Processing and Communications, Volume 8. New York: Hindawi Publishing Corporation, 2007. p. 93-112. ISBN: 978-977-454-001-1. Detail

  SLANÝ, K.; SEKANINA, L. Fitness Landscape Analysis and Image Filter Evolution Using Functional-Level CGP. Genetic Programming, 10th European Conference, EuroGP 2007. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2007. p. 311-320. ISBN: 978-3-540-71602-0. Detail

  STAREČEK, L.; SEKANINA, L.; GAJDA, Z.; KOTÁSEK, Z.; PROKOP, R.; MUSIL, V. On Properties and Utilization of Some Polymorphic Gates. 6th Electronic Circuits and Systems Conference (ECS 2007). Bratislava: Faculty of Informatics and Information Technology Slovak University of Technology in Bratislava, 2007. p. 77-81. ISBN: 978-80-227-2697-9. Detail

  VAŠÍČEK, Z.; SEKANINA, L. Evaluation of a New Platform For Image Filter Evolution. Proc. of the 2007 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2007. p. 577-584. ISBN: 076952866X. Detail

  VAŠÍČEK, Z.; SEKANINA, L. Reducing the Area on a Chip Using a Bank of Evolved Filters. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2007. p. 222-232. ISBN: 978-3-540-74625-6. Detail

  VAŠÍČEK, Z.; SEKANINA, L. An Evolvable Hardware System in Xilinx Virtex II Pro FPGA. International Journal of Innovative Computing and Applications, 2007, vol. 1, no. 1, p. 63-73. ISSN: 1751-648X. Detail

• 2006

  BIDLO, M.; BIDLO, R.; SEKANINA, L. Designing a Novel General Sorting Network Constructor Using Artificial Evolution. Transactions on Engineering, Computing and Technology, 2006, vol. 15, no. 10, p. 85-90. ISSN: 1305-5313. Detail

  BIDLO, M.; SEKANINA, L. Prostředky pro podporu vzdělávání v oblasti biologií inspirovaných výpočetních systémů. Pedagogický software 2006. České Budějovice: Scientifik Pedagogical Publishing, 2006. s. 81-83. ISBN: 80-85645-56-4. Detail

  PEČENKA, T.; KOTÁSEK, Z.; SEKANINA, L. FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties. Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006. p. 285-289. ISBN: 1424401844. Detail

  PEČENKA, T.; STRNADEL, J.; KOTÁSEK, Z.; SEKANINA, L. Testability Estimation Based on Controllability and Observability Parameters. Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06). IEEE CS. Cavtat: IEEE Computer Society, 2006. p. 504-514. ISBN: 0-7695-2609-8. Detail

  RŮŽIČKA, R.; SEKANINA, L. Evolutionary Circuit Design in REPOMO - Reconfigurable Polymorphic Module. Proceedings of the Second IASTED International Conference on Computational Intelligence. Anaheim: ACTA Press, 2006. p. 237-241. ISBN: 0-88986-602-3. Detail

  SEKANINA, L. Evolutionary Design of Digital Circuits: Where Are Current Limits?. Proc. of the 1st NASA/ESA Conference on Adaptive Hardware and Systems. Piscataway: IEEE Computer Society, 2006. p. 171-178. ISBN: 0-7695-2614-4. Detail

  SEKANINA, L. On Dependability of FPGA-Based Evolvable Hardware Systems That Utilize Virtual Reconfigurable Circuits. Computing Frontiers 2006 Conference. New York: Association for Computing Machinery, 2006. p. 221-228. ISBN: 1595933026. Detail

  SEKANINA, L.; MARTÍNEK, T.; GAJDA, Z. Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules. 2006 IEEE World Congress on Computational Intelligence. CA: IEEE Computational Intelligence Society, 2006. p. 9676-9683. ISBN: 0-7803-9489-5. Detail

  SEKANINA, L.; STAREČEK, L.; GAJDA, Z.; KOTÁSEK, Z. Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. Proc. of the 1st NASA/ESA Conference on Adaptive Hardware and Systems. Piscataway: IEEE Computer Society, 2006. p. 186-193. ISBN: 0-7695-2614-4. Detail

  SEKANINA, L.; STAREČEK, L.; KOTÁSEK, Z. Novel Logic Circuits Controlled by Vdd. Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006. p. 85-86. ISBN: 1424401844. Detail

  SEKANINA, L.; VAŠÍČEK, Z. On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level. Applications of Evolutionary Computing. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2006. p. 344-355. ISBN: 978-3-540-33237-4. Detail

  ZEBULUM, R.; KEYMEULEN, D.; RAMESHAM, R.; SEKANINA, L.; MAO, J.; KUMAR, N.; STOICA, A. Characterization and Synthesis of Circuits at Extreme Low Temperatures. In Evolvable Hardware. Genetic and Evolutionary Computation. Berlin: Springer Verlag, 2006. p. 161-172. ISBN: 0-387-24386-0. Detail

• 2005

  BIDLO, M.; SEKANINA, L. Providing Information from the Environment for Growing Electronic Circuits Through Polymorphic Gates. Proc. of Genetic and Evolutionary Computation Conference - Workshops 2005. New York: Association for Computing Machinery, 2005. p. 242-248. ISBN: 1-59593-097-3. Detail

  KOŘENEK, J.; SEKANINA, L. Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2005. p. 46-55. ISBN: 978-3-540-28736-0. Detail

  MARTÍNEK, T.; SEKANINA, L. An Evolvable Image Filter: Experimental Evaluation of a Complete Hardware Implementation in FPGA. In Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2005. p. 76-85. ISBN: 978-3-540-28736-0. Detail

  PEČENKA, T.; KOTÁSEK, Z.; SEKANINA, L.; STRNADEL, J. Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2005. p. 51-58. ISBN: 0-7695-2399-4. Detail

  SEKANINA, L. Design Methods for Polymorphic Digital Circuits. Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005. p. 145-150. ISBN: 9639364487. Detail

  SEKANINA, L. Evolutionary Design of Gate-Level Polymorphic Digital Circuits. Applications of Evolutionary Computation. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2005. p. 185-194. ISBN: 978-3-540-25396-9. Detail

  SEKANINA, L. Evoluční design poráží řešení vytvořená kreativním návrhářem. Vesmír, 2005, roč. 84, č. 1, s. 44-46. ISSN: 0042-4544. Detail

  SEKANINA, L.; BIDLO, M. Evolutionary Design of Arbitrarily Large Sorting Networks Using Development. Genetic Programming and Evolvable Machines, 2005, vol. 6, no. 3, p. 319-347. ISSN: 1389-2576. Detail

  SEKANINA, L.; ZEBULUM, R. Evolutionary discovering of the concept of the discrete state at the transistor level. Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2005. p. 73-78. ISBN: 0-7695-2399-4. Detail

  SEKANINA, L.; ZEBULUM, R. Intrinsic Evolution of Controllable Oscillators in FPTA-2. Evolvable Systems: From Biology to Hardware. Berlin: Springer Verlag, 2005. p. 98-107. ISBN: 978-3-540-28736-0. Detail

  ZEBULUM, R.; STOICA, A.; KEYMEULEN, D.; SEKANINA, L. Evolvable Hardware System at Extreme Low Temperatures. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2005. p. 37-45. ISBN: 978-3-540-28736-0. Detail

• 2004

  FRIEDL, Š.; SEKANINA, L. The First Circuits Evolved in a Physical Virtual Reconfigurable Device. Proc. of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Bratislava: Slovak Academy of Science, 2004. p. 35-42. ISBN: 80-969117-9-1. Detail

  KOTÁSEK, Z.; PEČENKA, T.; STRNADEL, J.; MIKA, D.; SEKANINA, L. An Overview of Research Activities in Digital Circuit Diagnosis and Benchmarking. Proceedings of the Sixth Internation Scientific Conference Electronic Computers nad Informatics 2004. Košice: The University of Technology Košice, 2004. p. 229-234. ISBN: 80-8073-150-0. Detail

  PEČENKA, T.; KOTÁSEK, Z.; SEKANINA, L.; STRNADEL, J. Evolutionary Design of Synthetic RTL Benchmark Circuits. Informal Digest of Papers, IEEE European Test Workshop 2004. Montpellier: IEEE Computer Society, 2004. p. 107-108. ISBN: 000000000. Detail

  RŮŽIČKA, R.; SEKANINA, L. A Platform for Demonstration of Analogue and Digital Circuits Evolution. Proceedings of the Sixth Internation Scientific Conference Electronic Computers nad Informatics 2004. Košice: The University of Technology Košice, 2004. p. 158-163. ISBN: 80-8073-150-0. Detail

  SEKANINA, L. Evolutionary Design Space Exploration for Median Circuits. Lecture Notes in Computer Science, 2004, vol. 2004, no. 3005, p. 240-249. ISSN: 0302-9743. Detail

  SEKANINA, L. Evolvable computing by means of evolvable components. Natural Computing, 2004, vol. 3, no. 3, p. 323-355. ISSN: 1567-7818. Detail

  SEKANINA, L. Evolving Constructors for Infinitely Growing Sorting Networks and Medians. Lecture Notes in Computer Science, 2004, vol. 2004, no. 2932, p. 314-323. ISSN: 0302-9743. Detail

  SEKANINA, L.; DRÁBEK, V. Theory and Applications of Evolvable Embedded Systems. Proc. of the 11th IEEE Int. Conference and Workshop on the Engineering of Computer-Based Systems. Los Alamitos, CA: IEEE Computer Society Press, 2004. p. 186-193. ISBN: 0-7695-2125-8. Detail

  SEKANINA, L.; FRIEDL, Š. On Routine Implementation of Virtual Evolvable Devices Using COMBO6. Proc. of the 2004 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2004. p. 63-70. ISBN: 0-7695-2145-2. Detail

  SEKANINA, L.; FRIEDL, Š. An Evolvable Combinational Unit for FPGAs. Computing and Informatics, 2004, vol. 23, no. 5, p. 461-486. ISSN: 1335-9150. Detail

  TORRESEN, J.; BAKKE, J.; SEKANINA, L. Efficient Image Filtering and Information Reduction in Reconfigurable Logic. Proc. of 2004 Norchip conference. Oslo: IEEE Computer Society Press, 2004. p. 63-66. ISBN: 0-7803-8510-1. Detail

  TORRESEN, J.; BAKKE, J.; SEKANINA, L. Efficient Recognition of Speed Limit Signs. Proc. of the 7th International IEEE Conference on Intelligent Transportation Systems. Los Alamos: IEEE Computer Society Press, 2004. p. 652-656. ISBN: 0-7803-8501-2. Detail

  TORRESEN, J.; BAKKE, J.; SEKANINA, L. Recognizing Speed Limit Sign Numbers by Evolvable Hardware. Lecture Notes in Computer Science, 2004, vol. 2004, no. 3242, p. 682-691. ISSN: 0302-9743. Detail

  VAŠÍČEK, Z.; SEKANINA, L. Evoluční návrh kombinačních obvodů. Elektrorevue - Internetový časopis (http://www.elektrorevue.cz), 2004, roč. 2004, č. 43, s. 1-6. ISSN: 1213-1539. Detail

• 2003

  RŮŽIČKA, R.; KOTÁSEK, Z.; SEKANINA, L. Sborník pracovního semináře "Počítačové architektury a diagnostika" pro studenty doktorského studia. Brno: Ústav počítačových systémů FIT VUT v Brně, 2003. s. 0-0. ISBN: 80-214-2471-0. Detail

  SEKANINA, L. Evolvable Components - From Theory to Hardware Implementations. Natural Computing Series. Natural Computing Series. Berlin: Springer Verlag, 2003. 194 p. ISBN: 3-540-40377-9. Detail

  SEKANINA, L. Towards Evolvable IP Cores for FPGAs. Proc. of The 2003 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2003. p. 145-154. ISBN: 0-7695-1977-6. Detail

  SEKANINA, L. From Implementations to a General Concept of Evolvable Machines. Lecture Notes in Computer Science, 2003, vol. 2003, no. 2610, p. 424-433. ISSN: 0302-9743. Detail

  SEKANINA, L. Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware. Lecture Notes in Computer Science, 2003, vol. 2003, no. 2606, p. 186-197. ISSN: 0302-9743. Detail

  SEKANINA, L.; RŮŽIČKA, R. Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers. The 2003 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2003. p. 135-144. ISBN: 0-7695-1977-6. Detail

  SEKANINA, L.; RŮŽIČKA, R. On the Automatic Design of Testable Circuits. Proceedings of IEEE Workshop on Design nad Diagnostics of Electronic Circuits and Systems. Poznań: Publishing House of Poznan University of Technology, 2003. p. 299-300. ISBN: 83-7143-557-6. Detail

• 2002

  DRÁBEK, V.; SEKANINA, L. Basic Principles of Bio-Inspired Approaches to Fault Tolerance: Tutorial. Design for Test of Systems on Chip: Digital Test. Tallinn: Tallinn University of Technology, 2002. p. 1-48. ISBN: 0000-00-000-0. Detail

  SEKANINA, L. Automata of Evolvable Computational Machines. Proc. ot 8th conference Student EEICT. Brno: Brno University of Technology, 2002. p. 491-495. ISBN: 80-214-2116-9. Detail

  SEKANINA, L. Evolution of digital circuits operating as image filters in dynamically changing environment. Mendel 2002 - 8th International Conference on Soft Computing. Brno: Brno University of Technology, 2002. p. 33-38. ISBN: 80-214-2135-5. Detail

  SEKANINA, L. Evolvable Computational Machines: Formal Approach. Intelligent Technologies - Theory and Applications, E-ISCI 2002. Frontiers in Artificial Intelligence and Applications. Amsterdam: IOS Press, 2002. p. 166-172. ISBN: 1-58603-256-9. Detail

  SEKANINA, L. Nanostructures and bio-inspired computer engineering (Abstract). Nano'02 (Abstracts). Brno: Akademické nakladatelství CERM, 2002. p. 74-74. ISBN: 80-7204-258-0. Detail

  SEKANINA, L. Nanostructures and bio-inspired computer engineering. Proceedings of Nano02. Ostrava: Repronis, 2002. p. 233-236. ISBN: 80-7329-027-8. Detail

  SEKANINA, L. Image Filter Design with Evolvable Hardware. Lecture Notes in Computer Science, 2002, vol. 2002, no. 2279, p. 255-266. ISSN: 0302-9743. Detail

  SEKANINA, L.; DRÁBEK, V. A Survey of Bioinspired Methods for Design of Fault Tolerant Reconfigurable Architectures. Proc. of the 8th Biennial Baltic Electronics Conference. Tallinn: Tallinn University of Technology, 2002. p. 355-358. ISBN: 9985-59-292-1. Detail

  SEKANINA, L.; DRÁBEK, V. Automatic Design of Image Operators Using Evolvable Hardware. Proc. of 5th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Brno: Brno University of Technology, 2002. p. 132-139. ISBN: 80-214-2094-4. Detail

  SEKANINA, L.; DRÁBEK, V. Soft-hardware. Vesmír, 2002, roč. 81, č. 7, s. 393-395. ISSN: 0042-4544. Detail

  SEKANINA, L.; TORRESEN, J. Detection of Norwegian Speed Limit Signs. Proc. of the 16th European Simulation Multiconference. Delft: SCS Publication House, 2002. p. 337-340. ISBN: 90-77039-07-4. Detail

  SLLAME, A.; SEKANINA, L. An Evolutionary-Based Algorithm to the Module Selection Problem with Resource Sharing in High-Level Synthesis. Advances in Nature-Inspired Computation: The PPSN VII Workshops. Reading: PEDAL, Department of Computer Science, University of Reading, 2002. p. 45-46. ISBN: 0-9543481-0-9. Detail

  SLLAME, A.; SEKANINA, L. An Evolutionary-Based Algorithm to the Module Selection Process in High-Level Synthesis. Mendel 2002 - 8th International Conference on Soft Computing. Brno: Brno University of Technology, 2002. p. 87-92. ISBN: 80-214-2135-5. Detail

• 2001

  SEKANINA, L.; DVOŘÁK, V. A Totally Distributed Genetic Algorithm: From a Cellular System to the Mesh of Processors. Modelling and Simulation 2001. Prague: Faculty of Electrical Engineering, Czech Technical University, 2001. p. 539-543. ISBN: 1-56555-225-3. Detail

• 2000

  RŮŽIČKA, R.; SEKANINA, L. The Role of Simulation During Design of Evolvable Systems. Proc. of 22-nd International Colloquium Advanced Simulation of Systems 2000. Ostrava: 2000. p. 85-90. ISBN: 80-85988-51-8. Detail

  SEKANINA, L. Components and Communications in Evolvable System. Sborník prací studentů a doktorandů. Brno: Akademické nakladatelství CERM, 2000. p. 231-233. ISBN: 80-7204-155-X. Detail

  SEKANINA, L.; DRÁBEK, V. Fault Tolerance and Reconfiguration in Cellular Systems. Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000. Smolenice: unknown, 2000. p. 134-137. ISBN: 80-968320-3-4. Detail

  SEKANINA, L.; DRÁBEK, V. Relation Between Fault Tolerance and Reconfiguration in Cellular Systems. 6th IEEE Int. On-Line Testing Workshop. Palma de Mallorca, Spain: IEEE Computer Society Press, 2000. p. 25-30. ISBN: 0-7695-0646-1. Detail

  SEKANINA, L.; DRÁBEK, V. The Concept of Pseudo Evolvable Hardware. IFAC Workshop on Programmable Devices and Systems 2000. Elsevier Science Ltd. Oxford: unknown, 2000. p. 0-0. ISBN: 0-08-043620-X. Detail

  SEKANINA, L.; RŮŽIČKA, R. Design of the Special Fast Reconfigurable Chip Using Common FPGA. Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000. Smolenice: unknown, 2000. p. 161-168. ISBN: 80-968320-3-4. Detail

  SEKANINA, L.; SLLAME, A. Toward Uniform Approach to Design of Evolvable Hardware Based Systems. Lecture Notes in Computer Science, 2000, vol. 2000, no. 1896, p. 814-817. ISSN: 0302-9743. Detail

  SLLAME, A.; SEKANINA, L. Simulation and Modeling of Evolvable Hardware Based Systems. MS2000 International Conference on Modeling and Simulation. Las Palmas de Gran Canaria: unknown, 2000. p. 485-492. ISBN: 84-95286-59-9. Detail

• 1999

  SEKANINA, L. Evolvable Hardware as Non-Linear Predictor for Image Compression. Proc. of the 2nd Prediction Conference Nostradamus'99. Zlín: unknown, 1999. p. 87-92. ISBN: 80-214-1424-3. Detail

  SEKANINA, L. Komprese obrazu s využitím modelu evolvable hardware. Konference Tvůrčí činnost studentů oboru VTI - TCS'99. Brno: Ústav informatiky a výpočetní techniky FEI VUT, 1999. s. 0-0. Detail

  SEKANINA, L. Komprese obrazu s využitím modelu evolvable hardware. In Sborník prací studentů a doktorandů, FEI VUT Brno. Brno: Akademické nakladatelství CERM sro., 1999. s. 103-104. ISBN: 80-214-1155-4. Detail

  SEKANINA, L.; DRÁBEK, V. Evolvable hardware - evoluce na čipu. Elektrorevue - Internetový časopis (http://www.elektrorevue.cz), 1999, roč. 1, č. 5, s. 0-0. ISSN: 1213-1539. Detail

• 1998

  SEKANINA, L. Model vyvíjejících se obvodů. In Sborník prací studentů a doktorandů, roč. IV, FEI VUT Brno. Brno: Akademické nakladatelství CERM sro., 1998. s. 61-62. ISBN: 80-214-1141-4. Detail