Ing.

Jiří Matyáš

Ph.D.

Member


imatyas@fit.vut.cz
A220 Office
156051/BUT personal ID

Publications

  • 2022

    ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; SEKANINA, L.; VAŠÍČEK, Z.; VOJNAR, T. SagTree: Towards Efficient Mutation in Evolutionary Circuit Approximation. Swarm and Evolutionary Computation, 2022, vol. 69, no. 100986, p. 1-10. ISSN: 2210-6502. Detail

    ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; VOJNAR, T. Designing Approximate Arithmetic Circuits with Combined Error Constraints. In Proceeding of 25th Euromicro Conference on Digital System Design 2022 (DSD'22). Gran Canaria: Institute of Electrical and Electronics Engineers, 2022. p. 785-792. ISBN: 978-1-6654-7404-7. Detail

  • 2020

    ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; SEKANINA, L.; VAŠÍČEK, Z.; VOJNAR, T. Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. APPLIED SOFT COMPUTING, 2020, vol. 95, no. 106466, p. 1-17. ISSN: 1568-4946. Detail

    ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; VOJNAR, T. Satisfiability Solving Meets Evolutionary Optimisation in Designing Approximate Circuits. In Theory and Applications of Satisfiability Testing - SAT 2020. Lecture Notes in Computer Science. Alghero: Springer International Publishing, 2020. p. 481-491. ISBN: 978-3-030-51824-0. Detail

    MATYÁŠ, J.; PANKUCH, A.; VOJNAR, T.; ČEŠKA, M.; ČEŠKA, M. Approximating Complex Arithmetic Circuits with Guaranteed Worst-Case Relative Error. In International Conference on Computer Aided Systems Theory (EUROCAST'19). Lecture Notes in Computer Science. Cham: Springer Verlag, 2020. p. 482-490. ISBN: 978-3-030-45092-2. Detail

  • 2018

    ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; VOJNAR, T. ADAC: Automated Design of Approximate Circuits. In Proceedings of 30th International Conference on Computer Aided Verification (CAV'18). Oxford, UK: Springer International Publishing, 2018. p. 612-620. ISBN: 978-3-319-96145-3. Detail

  • 2017

    ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; VOJNAR, T. Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished. In Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD). Irvine, CA: Institute of Electrical and Electronics Engineers, 2017. p. 416-423. ISBN: 978-1-5386-3093-8. Detail

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